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Re: [Patch ARM] Add support for bare-metal cpu initialization on A profile cores.
- From: Ramana Radhakrishnan <ramrad01 at arm dot com>
- To: Ye Joey <joey dot ye dot cc at gmail dot com>
- Cc: "newlib at sourceware dot org" <newlib at sourceware dot org>
- Date: Mon, 23 Sep 2013 10:25:55 +0100
- Subject: Re: [Patch ARM] Add support for bare-metal cpu initialization on A profile cores.
- Authentication-results: sourceware.org; auth=none
- References: <523AFD69 dot 8060701 at arm dot com> <CAL0py24Ju5gDg4LrfZJ9aCjheB9gRSfuAMGYxa8ZUGzdOVik2A at mail dot gmail dot com>
On 09/23/13 04:12, Ye Joey wrote:
This patch breaks combined build for Cortex-M, i.e., configured with
combine/src/libgloss/arm/cpu-init/rdimon-aem.S:84: Error: thumb
conditional instruction should be in IT block -- `moveq r4,#0'
I think when configured for M-profile, it shouldn't build rdimon-aem.S at all.
Ugggh ... sorry about the breakage.
Agreed - and something's off in the way in which we're multilibbing in
the cpu-init directory which is why I've not seen this.
The way I'm planning on fixing this is to
* Turn rdimon-aem.S into an empty file for M class cores.
* Force everything into ARM state anyway as it doesn't matter in T32
state whether one runs cpu-init in ARM or Thumb state.
Patch under testing.
On Thu, Sep 19, 2013 at 9:34 PM, Ramana Radhakrishnan <firstname.lastname@example.org> wrote:
Increasingly we've found the need for a start-up routine required
for bare-metal applications that need to initialize the mmu and the caches
for use during hardware bring-up and/or for bare-metal testing on ARM's
propreitary models as well as allow for semi-hosting to happen at the same
time. This has been found to be useful in a number of situations and this is
just the initial patch set required for this to work on A profile CPUs. I
would recommend that this not be used for earlier cores without testing.
The way this is implemented is by adding a new weak function called
_rdimon_init_hook that deals with this initialization. I expect this to work
on newer hardware because our testing involves testing with the AEM models
that model the newer hardware but I don't have access to any such hardware
to test this right now.
The SMP enable bit in the ACTLR is enabled only for A15 and A7 but not for
any other cores as this is needed only on those cores. We use this
internally for some of our GCC test runs on our fast models, we've tried it
in the past to run some simple applications on bare-metal A7 and A15 boards.
This necessitates the use of a new specs file aprofile-ve.specs which I've
added and provided as an example. I have tested this on an AEM model but am
confident that this will work just fine on a bare-metal board connected via
D-Stream or anything that implements the standard Angel API.
If people want to use a different base address for the text section and / or
for the vectors page in the cpu init code this is available by doing
--defsym _rdimon_vector_base=FOO or -Ttext_section=BAR . The specs file only
eases the use for this.
Tested with an arm-eabi bare-metal GCC multilib build across architecture
variants, Thumbness and fpu abi variants using the new specs file in my
baremetal build script and tested with --specs=aprofile-ve.specs passed by
default in my site.exp - tested on AEM VE model internally .
Ok to apply ?
<DATE> Matthew Gretton-Dann <email@example.com>
Ramana Radhakrishnan <firstname.lastname@example.org>
Greta Yorsh <email@example.com>
* arm/Makefile.in: Add support for cpu-init directory and add
* arm/configure.in: Likewise.
* arm/configure: Regenerate.
* arm/cpu-init: New directory.
* arm/cpu-init/Makefile.in: New file.
* arm/cpu-init/rdimon-aem.S: Likewise.
* arm/crt0.S: Call _rdimon_init_hook
* arm/elf-aprofile-ve.specs: New file.