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Re: [PATCH 0/9] RISC-V glibc port for the 32 bit
- From: Jim Wilson <jimw at sifive dot com>
- To: Zong Li <zong at andestech dot com>, joseph at codesourcery dot com, libc-alpha at sourceware dot org, palmer at dabbelt dot com, darius at bluespec dot com, andrew at sifive dot com, dj at redhat dot com
- Cc: zongbox at gmail dot com
- Date: Tue, 31 Jul 2018 11:49:26 -0700
- Subject: Re: [PATCH 0/9] RISC-V glibc port for the 32 bit
- Newsgroups: gmane.comp.lib.glibc.alpha
- References: <cover.1531384753.git.zong@andestech.com>
On 07/12/2018 03:26 AM, Zong Li wrote:
This patch set contains the glibc port for the 32 bit RISC-V. I ran the glibc
test suite on QEMU, and remained the failed cases which caused by environment
issue like 64 bit glibc port. In addition, there are some math test cases
need to be checked but it look unlike glibc's problem now.
There is an issue with the stat structure that should be resolved before
the 32-bit RISC-V port is upstreamed. I'm seeing failures with github
riscv/riscv-gnu-toolchain when building a riscv32-linux toolchain and
using a user-mode qemu for testing. There is some discussion here
https://github.com/riscv/riscv-gnu-toolchain/pull/325
and here
https://github.com/riscv/riscv-qemu/issues/135
The latter one suggests that we should first fix the 32-bit RISC-V linux
port to add
#define __ARCH_WANT_STAT64
to arch/include/riscv/asm/unistd.h, and then modify qemu, glibc, and
musl appropriately to match the kernel.
I don't have a riscv32-linux system I can boot, so I can't easily look
at this problem.
Jim