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Re: Any reason ARM doesn't implement sysconf.c?


On 31/10/17 15:30, Carlos O'Donell wrote:
> Is there any reason ARM doesn't implement sysconf.c? Too much
> hardware variance?
> 
> We've had at least a few user reports over the last year that
> things like sysconf (_SC_LEVEL1_DCACHE_SIZE); would be useful
> to have.
> 

i ok'd the patch
https://sourceware.org/ml/libc-alpha/2017-10/msg00395.html
but it seems it didnt get committed.

i was complaining about it at first because i think it was a
bad idea in the first place to introduce these undocumented
sysconf variables in glibc and then let users misuse it..
however there is a need to query the cache info that is
available to userspace on aarch64 and this api seems to be
what ppl expect.

the problem is not hardware variance but that the sysconf
names (l1/l2/l3 icache/dcache linesize) don't map to
architecture names (minimal i/dcache linesize, writeback
granule etc) that is userspace visible and have defined
semantics, the l1/l2/l3 cache info is not userspace
visible. (however Siddhesh wrote documentation for it now
so this is fine)

> On POWER this was generically fixed with some auxval entries
> that were passed down to userspace.
> 


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