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Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
- From: Siddhesh Poyarekar <siddhesh at gotplt dot org>
- To: Richard Henderson <rth at twiddle dot net>, Szabolcs Nagy <szabolcs dot nagy at arm dot com>, libc-alpha at sourceware dot org
- Cc: nd at arm dot com, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Wed, 11 Oct 2017 10:58:03 +0530
- Subject: Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
- Authentication-results: sourceware.org; auth=none
- References: <20170608225728.26779-1-rth@twiddle.net> <20170608225728.26779-2-rth@twiddle.net> <59DC9EC6.5080606@arm.com> <8fc9a891-aa77-2578-d450-1217c568e21c@twiddle.net>
On Tuesday 10 October 2017 07:50 PM, Richard Henderson wrote:
>> maybe
>
> Have you ever seen a system for which this was not true?
> I don't believe I have.
The Qualcomm Falkor chip shows the L2 dcache line size here instead of L1.
> They expect them to be exactly what they say they are.
> The question is, what do they expect to be able to do with that information.
>
> Speaking for myself, I expect to be able to dynamically align objects on this
> linesize and for that to have some predictable effect on performance.
This should continue to work well even for falkor. In fact, if a core
does this (i.e. deviate from L1 line size in ctr_el0) and also not
perform better (or at least not regress) then the designers should
understand that such a design would be sub-optimal.
Siddhesh