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Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
- From: Richard Henderson <rth at twiddle dot net>
- To: Szabolcs Nagy <szabolcs dot nagy at arm dot com>, libc-alpha at sourceware dot org
- Cc: nd at arm dot com, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Tue, 10 Oct 2017 07:20:32 -0700
- Subject: Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
- Authentication-results: sourceware.org; auth=none
- References: <20170608225728.26779-1-rth@twiddle.net> <20170608225728.26779-2-rth@twiddle.net> <59DC9EC6.5080606@arm.com>
On 10/10/2017 03:19 AM, Szabolcs Nagy wrote:
> On 08/06/17 23:57, Richard Henderson wrote:
>> + /* Unfortunately, the registers that contain the actual cache info
>> + (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
>> + kernel (though they need not have been). However, CTR_EL0 contains
>> + the *minimum* linesize in the entire cache hierarchy, and is
>> + accessible to userland, for use in __aarch64_sync_cache_range,
>> + and it is a reasonable assumption that the L1 cache will have that
>> + minimum line size. */
>
> maybe
Have you ever seen a system for which this was not true?
I don't believe I have.
>> + case _SC_LEVEL1_ICACHE_LINESIZE:
>> + case _SC_LEVEL1_DCACHE_LINESIZE:
>
> i can't find documentation for these, what meaning do users expect?
They expect them to be exactly what they say they are.
The question is, what do they expect to be able to do with that information.
Speaking for myself, I expect to be able to dynamically align objects on this
linesize and for that to have some predictable effect on performance.
r~