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Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
- From: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- To: Siddhesh Poyarekar <siddhesh at gotplt dot org>, libc-alpha at sourceware dot org
- Cc: nd at arm dot com
- Date: Tue, 10 Oct 2017 12:01:02 +0100
- Subject: Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
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On 10/10/17 11:37, Siddhesh Poyarekar wrote:
> On Tuesday 10 October 2017 03:49 PM, Szabolcs Nagy wrote:
>> On 08/06/17 23:57, Richard Henderson wrote:
>>> + case _SC_LEVEL1_ICACHE_LINESIZE:
>>> + case _SC_LEVEL1_DCACHE_LINESIZE:
>>
>> i can't find documentation for these, what meaning do users expect?
>
> Applications may use these hints to try and align their code/data
> suitably or read/write data in an optimal manner. It needs to be
that's different from the given libgcc clear_cache example
> documented and I hope to have a patch ready for it soon, but I wanted to
> be sure that this patch was in place since otherwise the documentation
> does not make sense.
either there is existing meaning or it's a new api with
some proposed meaning, i wanted to look at that to tell
if the implementation is acceptable.