RISC-V glibc Port v1

[Palmer Dabbelt <palmer at dabbelt dot com>]

We'd like to submit for inclusion in glibc a port for the RISC-V architecture.
While it is doubtlessly not complete, we think it is far enough along to start
the upstreaming process.  Our binutils and GCC ports have been accepted and
released.  Our Linux port was submitted a few weeks ago and is in the review
process, while it's not upstream yet the process seems to be going pretty well
and I anticipate RISC-V support will be merged by the 4.14 release.

This port targets Version 2.2 of the RISC-V User ISA, and supports both the
RV32I and RV64I base ISAs as well as the M, A, F, D, and C extensions as well
as our Linux port which is based on the 1.10 supervisor specification.  The
RISC-V community and the 60-some member companies of the RISC-V Foundation are
quite eager to have a single, standard glibc port.  We thank you in advance for
your help in this process and for your feedback on the software contribution
itself.

These patches build on top of master from sourceware's git repo from last
night, a65ea28d18 ("Make copy of <bits/std_abs.h> from GCC 7 [BZ #21573]").  We
have a handful of distributions chomping at the bit to begin porting to RISC-V
and we've asked them to hold off on this process until our glibc port is
upstream and released, as that's when our ABI will officially be stable.  As
such we're really hoping we can get this port in for the next release, which to
the best of my understanding will be 2.26 and should be relased in early
August.  Sorry if this is a bit late in the release process, but I'm hoping
it's still managable as our port doesn't touch any existing code outside of
config.h.in.

The one problem I know of in this port is that we want to put the atomic
compare and exchange system call in the VDSO so it can be implemented more
efficiently on kernels that support the A extension.  This is currently a work
in progress, but I wanted to try and submit these patches as soon as possible.
I'll include this change as part of the v2 patch set I assume I'll be
submitting.

Darius, Andrew and I will volunteer to maintain this port if it's OK with
everyone.  We have our FSF copyright assignment forms filled out via our
employers (SiFive for Andrew and I, BlueSpec for Darius).

We'd like to thank the various members of the RISC-V software community who
have helped us with the port.

I've attempted to split up the patches into small enough chunks that they would
get through the mailing list, but I haveted tested anything except the full
patch set (and I don't expect that to work at all).  In case anything gets
lost, our port can be found on Git Hub

  https://github.com/riscv/riscv-glibc/tree/riscv-for-submission-v1

[PATCH 01/12] RISC-V: Build Infastructure
[PATCH 02/12] RISC-V: ABI Implementation
[PATCH 03/12] RISC-V: Startup and Dynamic Loading Code
[PATCH 04/12] RISC-V: Thread-Local Storage Support
[PATCH 05/12] RISC-V: Generic <string.h> Routines
[PATCH 06/12] RISC-V: Generic <math.h> and soft-fp Routines
[PATCH 07/12] RISC-V: RV32F Support
[PATCH 08/12] RISC-V: RV32D, RV64F, and RV64D Support
[PATCH 09/12] RISC-V: Atomic and Locking Routines
[PATCH 10/12] RISC-V: Linux Syscall Interface
[PATCH 11/12] RISC-V: Linux ABI
[PATCH 12/12] RISC-V: Linux Startup and Dynamic Loading Code

Thanks!