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[PATCH] powerpc: Use lwsync on 64bit
- From: Anton Blanchard <anton at samba dot org>
- To: tuliom at linux dot vnet dot ibm dot com, cseo at linux dot vnet dot ibm dot com
- Cc: libc-alpha at sourceware dot org
- Date: Mon, 13 Feb 2017 10:22:20 +1100
- Subject: [PATCH] powerpc: Use lwsync on 64bit
- Authentication-results: sourceware.org; auth=none
Either an isync or an lwsync can be used as an acquire barrier after
a larx/stcx/bne sequence. All 64bit CPUs support lwsync and since the
isync instruction has other side effects that we don't need, use lwsync.
2017-02-12 Anton Blanchard <anton@samba.org>
* sysdeps/powerpc/atomic-machine.h: Allow __ARCH_ACQ_INSTR to be
overridden.
* sysdeps/powerpc/powerpc64/atomic-machine.h: define __ARCH_ACQ_INSTR
diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h
index 0a58203..31d67fa 100644
--- a/sysdeps/powerpc/atomic-machine.h
+++ b/sysdeps/powerpc/atomic-machine.h
@@ -57,7 +57,9 @@ typedef uintmax_t uatomic_max_t;
# define __ARCH_ACQ_INSTR ""
# define __ARCH_REL_INSTR ""
#else
-# define __ARCH_ACQ_INSTR "isync"
+# ifndef __ARCH_ACQ_INSTR
+# define __ARCH_ACQ_INSTR "isync"
+# endif
# ifndef __ARCH_REL_INSTR
# define __ARCH_REL_INSTR "sync"
# endif
diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h
index 40c308e..76c586a 100644
--- a/sysdeps/powerpc/powerpc64/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc64/atomic-machine.h
@@ -230,6 +230,7 @@
* "light weight" sync can also be used for the release barrier.
*/
#ifndef UP
+# define __ARCH_ACQ_INSTR "lwsync"
# define __ARCH_REL_INSTR "lwsync"
#endif
#define atomic_write_barrier() __asm ("lwsync" ::: "memory")