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Re: [RFC PATCH]: Align large allocations to cacheline
- From: Ryan Arnold <ryan dot arnold at linaro dot org>
- To: Wilco Dijkstra <wdijkstr at arm dot com>
- Cc: Andrew Pinski <pinskia at gmail dot com>, libc-alpha <libc-alpha at sourceware dot org>
- Date: Wed, 29 Oct 2014 10:03:51 -0500
- Subject: Re: [RFC PATCH]: Align large allocations to cacheline
- Authentication-results: sourceware.org; auth=none
- References: <002301cff37e$61c12330$25436990$ at com> <83C1311C-A583-4C97-A111-F8C0934D4AD4 at gmail dot com> <002401cff384$40254250$c06fc6f0$ at com>
On Wed, Oct 29, 2014 at 9:25 AM, Wilco Dijkstra <wdijkstr@arm.com> wrote:
>
> > Andrew Pinski wrote:
> >
> > > +#define MALLOC_LARGE_BLOCK_ALIGN (64)
> >
> > Yes that is not the only cache line size on aarch64. Why don't you make it a global variable
> > and read it from the system register like we do for memset? ThunderX has a cache line size of
> > 128.
>
> We could easily set it to 128 for AArch64 - the amount of wasted memory is
> minimal for large block sizes so overaligning doesn't hurt much.
>
> However you raise an interesting point - several functions may want to know
> the cacheline size and this would be useful across all targets. So we could
> add generic infrastructure that sets the cacheline size at GLIBC startup
> rather than having to add complex target specific code to compute it and
> cache it on demand in every function that might query the line size.
This has already done for powerpc since the A2 processor can use
different cache-line sizes, so look there for precedent.
grep for __cache_line_size.
--
Ryan S. Arnold
Linaro Toolchain Working Group - Engineering Manager
www.linaro.org