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RE: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
- From: Matthew Fortune <Matthew dot Fortune at imgtec dot com>
- To: Andy Lutomirski <luto at amacapital dot net>, Leonid Yegoshin <Leonid dot Yegoshin at imgtec dot com>
- Cc: David Daney <david dot s dot daney at gmail dot com>, Rich Felker <dalias at libc dot org>, David Daney <ddaney at caviumnetworks dot com>, David Daney <ddaney dot cavm at gmail dot com>, "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>, "linux-kernel at vger dot kernel dot org" <linux-kernel at vger dot kernel dot org>, "linux-mips at linux-mips dot org" <linux-mips at linux-mips dot org>, David Daney <david dot daney at cavium dot com>
- Date: Tue, 7 Oct 2014 19:40:27 +0000
- Subject: RE: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
- Authentication-results: sourceware.org; auth=none
- References: <1412627010-4311-1-git-send-email-ddaney dot cavm at gmail dot com> <20141006205459 dot GZ23797 at brightrain dot aerifal dot cx> <5433071B dot 4050606 at caviumnetworks dot com> <20141006213101 dot GA23797 at brightrain dot aerifal dot cx> <54330D79 dot 80102 at caviumnetworks dot com> <20141006215813 dot GB23797 at brightrain dot aerifal dot cx> <543327E7 dot 4020608 at amacapital dot net> <54332A64 dot 5020605 at caviumnetworks dot com> <20141007000514 dot GD23797 at brightrain dot aerifal dot cx> <543334CE dot 8060305 at caviumnetworks dot com> <20141007004915 dot GF23797 at brightrain dot aerifal dot cx> <54337127 dot 40806 at gmail dot com> <6D39441BF12EF246A7ABCE6654B0235320F1E173 at LEMAIL01 dot le dot imgtec dot org> <543431DA dot 4090809 at imgtec dot com> <CALCETrUQEbb=DotSzsneN7Hano_eC-EoTMko6uKcyZXvEcktkw at mail dot gmail dot com>
> >
> > 4) The voice for doing any instruction emulation in kernel - it is not a
> > MIPS business model to force customer to put details of all Coprocessor 2
> > instructions public. We provide an interface and the rest is a customer
> > business. Besides that it is really painful to make a differentiation
> > between Cavium Octeon and some another CPU instructions with the same
> > opcode. On other side, leaving emulation of their instructions to them is
> > not a wise after having some good way doing that multiple years.
>
> IMO this is all backwards. If MIPS customers put proprietary
> instructions into their ISA, they leave out the FPU, and they put a
> proprietary insn in a branch delay slot, then I think that they
> deserve a fatal signal.
>
> There's a really easy solution for new systems: fix the toolchain.
> Teach the assembler to disallow any proprietary instructions in an FP
> branch delay slot.
I think I'd be mostly in favour of this from a toolchain perspective but
only from the perspective of FP branch instructions. This still leaves a
problem for normal branches should any of them get removed and need emulating.
The general form of bltzal and bgezal would be the example here of branches
which are removed in R6 (The special case of using $0 remains). This is
really niche but my point is more about how we would deal with such a thing
if it happened. The answer may be just to scream and shout and discourage the
removal of such instructions from the architecture.
Matthew