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Re: [PATCH] Add a barrier in the double fma implementation
- From: Aurelien Jarno <aurelien at aurel32 dot net>
- To: Andreas Schwab <schwab at linux-m68k dot org>
- Cc: libc-alpha at sources dot redhat dot com, Joseph Myers <joseph at codesourcery dot com>
- Date: Thu, 16 Feb 2012 10:45:10 +0100
- Subject: Re: [PATCH] Add a barrier in the double fma implementation
- References: <20120215192056.GD17446@hall.aurel32.net><m2vcn7g2d0.fsf@igel.home>
On Wed, Feb 15, 2012 at 11:26:19PM +0100, Andreas Schwab wrote:
> Aurelien Jarno <aurelien@aurel32.net> writes:
>
> > --- a/sysdeps/ieee754/dbl-64/s_fma.c
> > +++ b/sysdeps/ieee754/dbl-64/s_fma.c
> > @@ -174,6 +174,8 @@
> > if ((u.ieee.mantissa1 & 1) == 0)
> > u.ieee.mantissa1 |= libc_fetestexcept (FE_INEXACT) != 0;
> > v.d = a1 + u.d;
> > + /* Ensure the addition is not scheduled after fetestexcept call. */
> > + asm volatile ("" : : "m" (v));
> math_force_eval (v.d);
>
Thanks for the review and for the hint. Please find a new version of the
patch below.
2012-02-16 Aurelien Jarno <aurelien@aurel32.net>
* sysdeps/ieee754/dbl-64/s_fma.c (__fma): Ensure a1 + u.d
computation is not scheduled after fetestexcept.
diff --git a/sysdeps/ieee754/dbl-64/s_fma.c b/sysdeps/ieee754/dbl-64/s_fma.c
index a27e246..d4ec834 100644
--- a/sysdeps/ieee754/dbl-64/s_fma.c
+++ b/sysdeps/ieee754/dbl-64/s_fma.c
@@ -1,5 +1,5 @@
/* Compute x * y + z as ternary operation.
- Copyright (C) 2010, 2011 Free Software Foundation, Inc.
+ Copyright (C) 2010, 2011, 2012 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Jakub Jelinek <jakub@redhat.com>, 2010.
@@ -173,6 +173,8 @@ __fma (double x, double y, double z)
if ((u.ieee.mantissa1 & 1) == 0)
u.ieee.mantissa1 |= libc_fetestexcept (FE_INEXACT) != 0;
v.d = a1 + u.d;
+ /* Ensure the addition is not scheduled after fetestexcept call. */
+ math_force_eval (v.d);
int j = libc_fetestexcept (FE_INEXACT) != 0;
libc_feupdateenv (&env);
/* Ensure the following computations are performed in default rounding
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net