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[SH][PATCH] SH4 NOFPU support
- From: Andrew Stubbs <ams at codesourcery dot com>
- To: libc-alpha at sources dot redhat dot com
- Date: Thu, 29 Jan 2009 14:51:09 +0000
- Subject: [SH][PATCH] SH4 NOFPU support
At present, building for SH4 with the FPU disabled fails with illegal
instruction errors from the assembler.
Please apply this patch to fix the issues. Mostly it's just a matter of
conditional compilation/assembly. I have added only a very small amount
of new code.
Thanks
Andrew Stubbs
2009-01-29 Andrew Stubbs <ams@codesourcery.com>
glibc/
* sysdeps/sh/dl-trampoline.S: HAVE_FPU -> !__SH4_NOFPU__
* sysdeps/sh/sh4/setjmp.S: Support SH4-NOFPU.
* sysdeps/sh/sh4/__longjmp.S: Likewise.
* sysdeps/unix/sysv/linux/sh/sh4/getcontext.S: Likewise.
* sysdeps/unix/sysv/linux/sh/sh4/setcontext.S: Likewise.
* sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S: Likewise.
* sysdeps/unix/sysv/linux/sh/sh4/register-dump.h: Likewise.
---
src/glibc-mainline/sysdeps/sh/dl-trampoline.S | 16 +++++-----
src/glibc-mainline/sysdeps/sh/sh4/__longjmp.S | 5 +++
src/glibc-mainline/sysdeps/sh/sh4/setjmp.S | 2 +
src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S | 2 +
src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/register-dump.h | 2 +
src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S | 2 +
src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S | 4 ++
7 files changed, 25 insertions(+), 8 deletions(-)
Index: src/glibc-mainline/sysdeps/sh/dl-trampoline.S
===================================================================
--- src/glibc-mainline/sysdeps/sh/dl-trampoline.S.orig
+++ src/glibc-mainline/sysdeps/sh/dl-trampoline.S
@@ -46,7 +46,7 @@ _dl_runtime_resolve:
movt r3 ! Save T flag.
mov.l r3,@-r15
cfi_adjust_cfa_offset (4)
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
sts.l fpscr,@-r15
cfi_adjust_cfa_offset (4)
mov #8,r3
@@ -90,7 +90,7 @@ _dl_runtime_resolve:
mov r1,r6 ! reloc offset
lds.l @r15+,pr ! Get register content back.
cfi_adjust_cfa_offset (-4)
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
fmov.s @r15+,fr4
cfi_adjust_cfa_offset (-4)
fmov.s @r15+,fr5
@@ -150,7 +150,7 @@ _dl_runtime_resolve:
_dl_runtime_profile:
mov.l r12,@-r15
cfi_adjust_cfa_offset (4)
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
sts.l fpscr,@-r15
cfi_adjust_cfa_offset (4)
mov #8,r12
@@ -253,7 +253,7 @@ _dl_runtime_profile:
cfi_adjust_cfa_offset (-4)
mov.l @r15+,r7
cfi_adjust_cfa_offset (-4)
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
fmov.s @r15+,fr4
cfi_adjust_cfa_offset (-4)
fmov.s @r15+,fr5
@@ -315,7 +315,7 @@ _dl_runtime_profile:
mov.l @r12+,r5
mov.l @r12+,r6
mov.l @r12+,r7
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
fmov.s @r12+,fr4
fmov.s @r12+,fr5
fmov.s @r12+,fr6
@@ -334,7 +334,7 @@ _dl_runtime_profile:
mov.l @(12,r15),r4 ! link map address
mov.l @(16,r15),r5 ! reloc offset
mov.l @r15,r6 ! input registers
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
mov #16,r8
add r15,r8
fmov.s fr1,@-r8
@@ -362,7 +362,7 @@ _dl_runtime_profile:
cfi_adjust_cfa_offset (-4)
mov.l @r15+,r1
cfi_adjust_cfa_offset (-4)
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
fmov.s @r15+,fr0
cfi_adjust_cfa_offset (-4)
fmov.s @r15+,fr1
@@ -394,7 +394,7 @@ _dl_runtime_profile:
cfi_adjust_cfa_offset (-4)
mov.l @r15+,r7
cfi_adjust_cfa_offset (-4)
-#ifdef HAVE_FPU
+#ifndef __SH4_NOFPU__
fmov.s @r15+,fr4
cfi_adjust_cfa_offset (-4)
fmov.s @r15+,fr5
Index: src/glibc-mainline/sysdeps/sh/sh4/__longjmp.S
===================================================================
--- src/glibc-mainline/sysdeps/sh/sh4/__longjmp.S.orig
+++ src/glibc-mainline/sysdeps/sh/sh4/__longjmp.S
@@ -52,6 +52,7 @@ ENTRY (__longjmp)
mov.l @r4+, r15
lds.l @r4+, pr
#endif
+#ifndef __SH4_NOFPU__
ldc.l @r4+, gbr
lds.l @r4+, fpscr
fmov.s @r4+, fr12
@@ -59,4 +60,8 @@ ENTRY (__longjmp)
fmov.s @r4+, fr14
rts
fmov.s @r4+, fr15
+#else
+ rts
+ ldc.l @r4+, gbr
+#endif /* !__SH4_NOFPU__ */
END (__longjmp)
Index: src/glibc-mainline/sysdeps/sh/sh4/setjmp.S
===================================================================
--- src/glibc-mainline/sysdeps/sh/sh4/setjmp.S.orig
+++ src/glibc-mainline/sysdeps/sh/sh4/setjmp.S
@@ -23,11 +23,13 @@
ENTRY (__sigsetjmp)
/* Save registers */
add #JB_SIZE, r4
+#ifndef __SH4_NOFPU__
fmov.s fr15, @-r4
fmov.s fr14, @-r4
fmov.s fr13, @-r4
fmov.s fr12, @-r4
sts.l fpscr, @-r4
+#endif /* !__SH4_NOFPU__ */
stc.l gbr, @-r4
#ifdef PTR_MANGLE
sts pr, r2
Index: src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S
===================================================================
--- src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S.orig
+++ src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/getcontext.S
@@ -61,6 +61,7 @@ ENTRY(__getcontext)
mov.l r9, @-r0
mov.l r8, @-r0
+#ifndef __SH4_NOFPU__
mov r4, r0
/* We need 2 add instruction because oFPUL+4 > 127. */
add #124,r0
@@ -101,6 +102,7 @@ ENTRY(__getcontext)
fmov.s fr2, @-r0
fmov.s fr1, @-r0
fmov.s fr0, @-r0
+#endif /* !__SH4_NOFPU__ */
/* sigprocmask (SIG_BLOCK, NULL, &uc->uc_sigmask). */
mov r4, r6
Index: src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/register-dump.h
===================================================================
--- src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/register-dump.h.orig
+++ src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/register-dump.h
@@ -144,6 +144,7 @@ register_dump (int fd, struct sigcontext
ADD_STRING ("\n");
+#ifndef __SH4_NOFPU__
if (ctx->sc_ownedfp != NULL)
{
hexvalue (ctx->sc_fpregs[0], fpregs[0], 8);
@@ -253,6 +254,7 @@ register_dump (int fd, struct sigcontext
ADD_STRING ("\n");
}
+#endif /* !__SH4_NOFPU__ */
/* Write the stuff out. */
writev (fd, iov, nr);
Index: src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S
===================================================================
--- src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S.orig
+++ src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/setcontext.S
@@ -50,6 +50,7 @@ ENTRY(__setcontext)
nop
.Lsetcontext_restore:
+#ifndef __SH4_NOFPU__
mov r8, r0
add #(oFR0),r0
fmov.s @r0+, fr0
@@ -88,6 +89,7 @@ ENTRY(__setcontext)
frchg
lds.l @r0+, fpscr
lds.l @r0+, fpul
+#endif /* !__SH4_NOFPU__ */
mov r8, r0
add #(oPC), r0
Index: src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S
===================================================================
--- src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S.orig
+++ src/glibc-mainline/sysdeps/unix/sysv/linux/sh/sh4/swapcontext.S
@@ -61,6 +61,7 @@ ENTRY(__swapcontext)
mov.l r9, @-r0
mov.l r8, @-r0
+#ifndef __SH4_NOFPU__
mov r4, r0
/* We need 2 add instruction because oFPUL+4 >= 127. */
add #124,r0
@@ -101,6 +102,7 @@ ENTRY(__swapcontext)
fmov.s fr2, @-r0
fmov.s fr1, @-r0
fmov.s fr0, @-r0
+#endif /* !__SH4_NOFPU__ */
mov r5, r8
@@ -125,6 +127,7 @@ ENTRY(__swapcontext)
rts
nop
.Lswapcontext_restore:
+#ifndef __SH4_NOFPU__
mov r8, r0
add #(oFR0),r0
fmov.s @r0+, fr0
@@ -163,6 +166,7 @@ ENTRY(__swapcontext)
frchg
lds.l @r0+, fpscr
lds.l @r0+, fpul
+#endif /* !__SH4_NOFPU__ */
mov r8, r0
add #(oPC), r0