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Re: Adding m32-linux support glibc again.


I replaced them.

Thanks,
Kazuhiro Inaoka

Roland McGrath wrote:

2004-09-09 Kazuhiro Inaoka <inaoka dot kazuhiro at renesas dot com>


Put this in standard format.


	* stdlib/longlong.h (add_ssaaaa, sub_ddmmss): Fixed miss
	operands.


I'm not sure what this sentence is supposed to mean.


+ #define R_M32R_16 1 /* For backwards compatibility. */


Can you replace all the comments that say this with comments describing the
meaning of the code?


Thanks, Roland


libc/ChangeLog


2004-09-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>

	* stdlib/longlong.h (add_ssaaaa, sub_ddmmss): Fix macros for
	m32r add_ssaaaa and sub_ddmmss.
	* elf/elf.h: Add m32r relocs.


Index: elf.h
===================================================================
RCS file: /cvs/glibc/libc/elf/elf.h,v
retrieving revision 1.140
diff -c -r1.140 elf.h
*** elf.h	7 May 2004 01:56:25 -0000	1.140
--- elf.h	10 Sep 2004 01:53:49 -0000
***************
*** 2462,2467 ****
--- 2462,2522 ----
  
  #define R_X86_64_NUM		24
  
+ /* M32R relocs.  */
+ #define R_M32R_NONE		0	/* No reloc. */
+ #define R_M32R_16		1	/* Direct 16 bit. */
+ #define R_M32R_32		2	/* Direct 32 bit. */
+ #define R_M32R_24		3	/* Direct 24 bit. */
+ #define R_M32R_10_PCREL		4	/* PC relative 10 bit shifted. */
+ #define R_M32R_18_PCREL		5	/* PC relative 18 bit shifted. */
+ #define R_M32R_26_PCREL		6	/* PC relative 26 bit shifted. */
+ #define R_M32R_HI16_ULO		7	/* High 16 bit with unsigned low. */
+ #define R_M32R_HI16_SLO		8	/* High 16 bit with signed low. */
+ #define R_M32R_LO16		9	/* Low 16 bit. */
+ #define R_M32R_SDA16		10	/* 16 bit offset in SDA. */
+ #define R_M32R_GNU_VTINHERIT	11
+ #define R_M32R_GNU_VTENTRY	12
+ /* M32R relocs.use SHT_RELA */
+ #define R_M32R_16_RELA		33	/* Direct 16 bit. */
+ #define R_M32R_32_RELA		34	/* Direct 32 bit. */
+ #define R_M32R_24_RELA		35	/* Direct 24 bit. */
+ #define R_M32R_10_PCREL_RELA	36	/* PC relative 10 bit shifted. */
+ #define R_M32R_18_PCREL_RELA	37	/* PC relative 18 bit shifted. */
+ #define R_M32R_26_PCREL_RELA	38	/* PC relative 26 bit shifted. */
+ #define R_M32R_HI16_ULO_RELA	39	/* High 16 bit with unsigned low */
+ #define R_M32R_HI16_SLO_RELA	40	/* High 16 bit with signed low */
+ #define R_M32R_LO16_RELA	41	/* Low 16 bit */
+ #define R_M32R_SDA16_RELA	42	/* 16 bit offset in SDA */
+ #define R_M32R_RELA_GNU_VTINHERIT	43
+ #define R_M32R_RELA_GNU_VTENTRY	44
+ 
+ #define R_M32R_GOT24		48	/* 24 bit GOT entry */
+ #define R_M32R_26_PLTREL	49	/* 26 bit PC relative to PLT shifted */
+ #define R_M32R_COPY		50	/* Copy symbol at runtime */
+ #define R_M32R_GLOB_DAT		51	/* Create GOT entry */
+ #define R_M32R_JMP_SLOT		52	/* Create PLT entry */
+ #define R_M32R_RELATIVE		53	/* Adjust by program base */
+ #define R_M32R_GOTOFF		54	/* 24 bit offset to GOT */
+ #define R_M32R_GOTPC24		55	/* 24 bit PC relative offset to GOT */
+ #define R_M32R_GOT16_HI_ULO	56	/* High 16 bit GOT entry with unsigned
+ 					   low */
+ #define R_M32R_GOT16_HI_SLO	57	/* High 16 bit GOT entry with signed
+ 					   low */
+ #define R_M32R_GOT16_LO		58	/* Low 16 bit GOT entry */
+ #define R_M32R_GOTPC_HI_ULO	59	/* High 16 bit PC relative offset to
+ 					   GOT with unsigned low */
+ #define R_M32R_GOTPC_HI_SLO	60	/* High 16 bit PC relative offset to
+ 					   GOT with signed low */
+ #define R_M32R_GOTPC_LO		61	/* Low 16 bit PC relative offset to
+ 					   GOT */
+ #define R_M32R_GOTOFF_HI_ULO	62	/* High 16 bit offset to GOT
+ 					   with unsigned low */
+ #define R_M32R_GOTOFF_HI_SLO	63	/* High 16 bit offset to GOT
+ 					   with signed low */
+ #define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
+ /* Keep this the last entry. */
+ #define R_M32R_NUM		256
+ 
  __END_DECLS
  
  #endif	/* elf.h */
*** ../libc-org/stdlib/longlong.h	2002-09-29 21:34:54.000000000 +0900
--- ./stdlib/longlong.h	2004-06-14 19:03:05.000000000 +0900
***************
*** 400,416 ****
  #if defined (__M32R__) && W_TYPE_SIZE == 32
  #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
    /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"			\
  	   : "=r" ((USItype) (sh)),					\
  	     "=&r" ((USItype) (sl))					\
! 	   : "%0" ((USItype) (ah)),					\
  	     "r" ((USItype) (bh)),					\
! 	     "%1" ((USItype) (al)),					\
  	     "r" ((USItype) (bl))					\
  	   : "cbit")
  #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
    /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"			\
  	   : "=r" ((USItype) (sh)),					\
  	     "=&r" ((USItype) (sl))					\
  	   : "0" ((USItype) (ah)),					\
--- 400,416 ----
  #if defined (__M32R__) && W_TYPE_SIZE == 32
  #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
    /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
  	   : "=r" ((USItype) (sh)),					\
  	     "=&r" ((USItype) (sl))					\
! 	   : "0" ((USItype) (ah)),					\
  	     "r" ((USItype) (bh)),					\
! 	     "1" ((USItype) (al)),					\
  	     "r" ((USItype) (bl))					\
  	   : "cbit")
  #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
    /* The cmp clears the condition bit.  */ \
!   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
  	   : "=r" ((USItype) (sh)),					\
  	     "=&r" ((USItype) (sl))					\
  	   : "0" ((USItype) (ah)),					\

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