[glibc/ibm/2.30/master] [powerpc] __fesetround_inline optimizations

[Paul Clarke <pc at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=8a7b3df72dc489a62d8a42a389fd2408c63056a4

commit 8a7b3df72dc489a62d8a42a389fd2408c63056a4
Author: Paul A. Clarke <pc@us.ibm.com>
Date:   Thu Sep 19 11:39:44 2019 -0500

    [powerpc] __fesetround_inline optimizations
    
    On POWER9, use more efficient means to update the 2-bit rounding mode
    via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions
    or one 'mtfsfi' instruction that modifies 4 bits).
    
    Suggested-by: Paul E. Murphy  <murphyp@linux.ibm.com>
    Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>

Diff:
---
 ChangeLog                       |  6 ++++++
 sysdeps/powerpc/fpu/fenv_libc.h | 18 +++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/ChangeLog b/ChangeLog
index 5fde58a..5a53b92 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,11 @@
 2019-09-27  Paul A. Clarke  <pc@us.ibm.com>
 
+	* sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use
+	'mffscrn' instruction on POWER9.
+	(__fesetround_inline_nocheck): Likewise.
+
+2019-09-27  Paul A. Clarke  <pc@us.ibm.com>
+
 	* sysdeps/powerpc/fpu/fenv_libc.h (FPSCR_EXCEPTIONS_MASK):  New.
 	* sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc):  Optimize
 	to write FPSCR control only, if exceptions have not changed.
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index 38ab6cd..4aad792 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -148,7 +148,12 @@ typedef union
 static inline int
 __fesetround_inline (int round)
 {
-  if ((unsigned int) round < 2)
+#ifdef _ARCH_PWR9
+  __fe_mffscrn (round);
+#else
+  if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
+    __fe_mffscrn (round);
+  else if ((unsigned int) round < 2)
     {
        asm volatile ("mtfsb0 30");
        if ((unsigned int) round == 0)
@@ -164,7 +169,7 @@ __fesetround_inline (int round)
        else
          asm volatile ("mtfsb1 31");
     }
-
+#endif
   return 0;
 }
 
@@ -173,7 +178,14 @@ __fesetround_inline (int round)
 static inline void
 __fesetround_inline_nocheck (const int round)
 {
-  asm volatile ("mtfsfi 7,%0" : : "i" (round));
+#ifdef _ARCH_PWR9
+  __fe_mffscrn (round);
+#else
+  if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00))
+    __fe_mffscrn (round);
+  else
+    asm volatile ("mtfsfi 7,%0" : : "i" (round));
+#endif
 }
 
 #define FPSCR_MASK(bit) (1 << (31 - (bit)))