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GNU C Library master sources branch master updated. glibc-2.26.9000-637-ga2e0a7f
- From: siddhesh at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 23 Oct 2017 14:54:46 -0000
- Subject: GNU C Library master sources branch master updated. glibc-2.26.9000-637-ga2e0a7f
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http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347
commit a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347
Author: Siddhesh Poyarekar <siddhesh@sourceware.org>
Date: Mon Oct 23 20:22:42 2017 +0530
aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat
The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the
ctr_el0 register, which tells us the minimum observable cache line
size by userspace. This typically is the same as the L1 cache line
size, but that may not always be true. It could be a higher level
cache line size as long as cache cleaning and invalidation work
correctly with that line size in userspace. The falkor core for
example reports the L2 line size as the dcache line size in CTR_EL0
while also reporting the correct L1 dcache line size via CCSIDR_EL1.
* manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
_SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
Reviewed-by: Rical Jasan <ricaljasan@pacific.net>
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
diff --git a/ChangeLog b/ChangeLog
index 8904437..b756f97 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,8 @@
2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org>
+ * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE,
+ _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat.
+
* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
diff --git a/manual/conf.texi b/manual/conf.texi
index 079bdb2..62ab444 100644
--- a/manual/conf.texi
+++ b/manual/conf.texi
@@ -690,6 +690,12 @@ Inquire about the associativity of the Level 1 instruction cache.
@standards{GNU, unistd.h}
Inquire about the line length of the Level 1 instruction cache.
+On aarch64, the cache line size returned is the minimum instruction cache line
+size observable by userspace. This is typically the same as the L1 icache
+size but on some cores it may not be so. However, it is specified in the
+architecture that operations such as cache line invalidation are consistent
+with the size reported with this variable.
+
@item _SC_LEVEL1_DCACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 1 data cache.
@@ -702,6 +708,12 @@ Inquire about the associativity of the Level 1 data cache.
@standards{GNU, unistd.h}
Inquire about the line length of the Level 1 data cache.
+On aarch64, the cache line size returned is the minimum data cache line size
+observable by userspace. This is typically the same as the L1 dcache size but
+on some cores it may not be so. However, it is specified in the architecture
+that operations such as cache line invalidation are consistent with the size
+reported with this variable.
+
@item _SC_LEVEL2_CACHE_SIZE
@standards{GNU, unistd.h}
Inquire about the size of the Level 2 cache.
http://sourceware.org/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=db9bab09a51188bf57afeb47040ce6837b878367
commit db9bab09a51188bf57afeb47040ce6837b878367
Author: Siddhesh Poyarekar <siddhesh@sourceware.org>
Date: Mon Oct 23 20:19:34 2017 +0530
Document cache information sysconf variables
Write short descriptions for each of the cache information sysconf
variables.
* manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
_SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
_SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
_SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
_SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
_SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
_SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
variables.
Reviewed-by: Rical Jasan <ricaljasan@pacific.net>
diff --git a/ChangeLog b/ChangeLog
index 1316b40..8904437 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,15 @@
+2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org>
+
+ * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE,
+ _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE,
+ _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC,
+ _SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE,
+ _SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE,
+ _SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC,
+ _SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE,
+ _SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New
+ variables.
+
2017-10-23 Michael Collison <michael.collison@arm.com>
* sysdeps/aarch64/fpu/e_sqrt.c (ieee754_sqrt): Replace asm statements
diff --git a/manual/conf.texi b/manual/conf.texi
index 875862c..079bdb2 100644
--- a/manual/conf.texi
+++ b/manual/conf.texi
@@ -678,6 +678,67 @@ Inquire about the number of available physical pages in the system.
Inquire about the number of functions which can be registered as termination
functions for @code{atexit}; @pxref{Cleanups on Exit}.
+@item _SC_LEVEL1_ICACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 1 instruction cache.
+
+@item _SC_LEVEL1_ICACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about the associativity of the Level 1 instruction cache.
+
+@item _SC_LEVEL1_ICACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 1 instruction cache.
+
+@item _SC_LEVEL1_DCACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 1 data cache.
+
+@item _SC_LEVEL1_DCACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about the associativity of the Level 1 data cache.
+
+@item _SC_LEVEL1_DCACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 1 data cache.
+
+@item _SC_LEVEL2_CACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 2 cache.
+
+@item _SC_LEVEL2_CACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about the associativity of the Level 2 cache.
+
+@item _SC_LEVEL2_CACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 2 cache.
+
+@item _SC_LEVEL3_CACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 3 cache.
+
+@item _SC_LEVEL3_CACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about the associativity of the Level 3 cache.
+
+@item _SC_LEVEL3_CACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 3 cache.
+
+@item _SC_LEVEL4_CACHE_SIZE
+@standards{GNU, unistd.h}
+Inquire about the size of the Level 4 cache.
+
+@item _SC_LEVEL4_CACHE_ASSOC
+@standards{GNU, unistd.h}
+Inquire about the associativity of the Level 4 cache.
+
+@item _SC_LEVEL4_CACHE_LINESIZE
+@standards{GNU, unistd.h}
+Inquire about the line length of the Level 4 cache.
+
+
@item _SC_XOPEN_VERSION
@standards{X/Open, unistd.h}
Inquire about the parameter corresponding to @code{_XOPEN_VERSION}.
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 15 +++++++++++
manual/conf.texi | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 88 insertions(+), 0 deletions(-)
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