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GNU C Library master sources branch master updated. glibc-2.16-ports-merge-605-g0244426
- From: cmetcalf at sourceware dot org
- To: glibc-cvs at sourceware dot org
- Date: 3 Nov 2012 12:46:32 -0000
- Subject: GNU C Library master sources branch master updated. glibc-2.16-ports-merge-605-g0244426
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- Log -----------------------------------------------------------------
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=0244426b930b006b128ea0c874b1301e9528ad5f
commit 0244426b930b006b128ea0c874b1301e9528ad5f
Author: Chris Metcalf <cmetcalf@tilera.com>
Date: Sat Nov 3 08:46:09 2012 -0400
tile: Account for new tests (missed test-double changes)
diff --git a/ports/ChangeLog.tile b/ports/ChangeLog.tile
index 1f04349..059e2f8 100644
--- a/ports/ChangeLog.tile
+++ b/ports/ChangeLog.tile
@@ -1,3 +1,7 @@
+2012-11-03 Chris Metcalf <cmetcalf@tilera.com>
+
+ * sysdeps/tile/libm-test-ulps: Account for new tests.
+
2012-10-30 Chris Metcalf <cmetcalf@tilera.com>
* sysdeps/tile/dl-machine.h: Use new DL_AFTER_LOAD macro
diff --git a/ports/sysdeps/tile/libm-test-ulps b/ports/sysdeps/tile/libm-test-ulps
index 0187d5a..584e570 100644
--- a/ports/sysdeps/tile/libm-test-ulps
+++ b/ports/sysdeps/tile/libm-test-ulps
@@ -602,8 +602,10 @@ Test "Real part of: clog10 (0.75 + 1.25 i) == 0.16367946719316517144947660507742
float: 1
ifloat: 1
Test "Real part of: clog10 (0x0.fffffffffffff8p0 + 0x0.fffffffffffff8p-1000 i) == -4.821637332766435821255375046554377090472e-17 + 4.053112396770095089737411317782466262176e-302 i":
+double: 1
idouble: 1
Test "Real part of: clog10 (0x0.ffffffp0 + 0x0.ffffffp-100 i) == -2.588596909321764128428416045209904492216e-8 + 3.425979381266895667295625489912064603415e-31 i":
+double: 1
float: 2
idouble: 1
ifloat: 2
@@ -634,14 +636,19 @@ Test "Real part of: clog10 (0x1.fffffep+127 + 1.0 i) == 38.531839419103623894140
float: 1
ifloat: 1
Test "Real part of: clog10 (0x10673dd0f2481p-51 + 0x7ef1d17cefbd2p-51 i) == 1.3918041236396763648388478552321724382899e-29 + 0.6263795733790237053262025311642907438291 i":
+double: 1
idouble: 1
Test "Real part of: clog10 (0x1367a310575591p-54 + 0x3cfcc0a0541f60p-54 i) == 2.2081507730821788480616336165447731164865e-32 + 0.5484039935757001196548030312819898864760 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0x1367a310575591p-54 + 0x3cfcc0a0541f60p-54 i) == 2.2081507730821788480616336165447731164865e-32 + 0.5484039935757001196548030312819898864760 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0x164c74eea876p-45 + 0x16f393482f77p-45 i) == -1.3155760824064879362415202279780039150764e-26 + 0.3473590599762514228227328130640352044313 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0x1a6p-10 + 0x3a5p-10 i) == -6.2126412844802358329771948751248003038444e-07 + 0.4977135139537443711784513409096950995985 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0x1p-1074 + 0x1.fp+1023 i) == 308.2409272754311106024666378243768099991 + 0.6821881769209206737428918127156778851051 i":
double: 1
@@ -693,6 +700,7 @@ float: 1
idouble: 1
ifloat: 1
Test "Real part of: clog10 (0x2818p-15 + 0x798fp-15 i) == 6.6737261053986614395049481326819059203910e-09 + 0.5438241985991753781478398141908629586460 i":
+double: 1
float: 1
idouble: 1
ifloat: 1
@@ -700,23 +708,31 @@ Test "Imaginary part of: clog10 (0x2818p-15 + 0x798fp-15 i) == 6.673726105398661
float: 1
ifloat: 1
Test "Real part of: clog10 (0x2dd46725bp-35 + 0x7783a1284p-35 i) == 1.9312741086596516918394613098872836703188e-20 + 0.5231613813514771042838490538484014771862 i":
+double: 1
idouble: 1
Test "Real part of: clog10 (0x2ede88p-23 + 0x771c3fp-23 i) == -1.9440841725722970687903291200493082253766e-13 + 0.5193774116724956222518530053006822210323 i":
float: 1
ifloat: 1
Test "Imaginary part of: clog10 (0x2ede88p-23 + 0x771c3fp-23 i) == -1.9440841725722970687903291200493082253766e-13 + 0.5193774116724956222518530053006822210323 i":
+double: 1
idouble: 1
Test "Real part of: clog10 (0x4447d7175p-35 + 0x6c445e00ap-35 i) == -6.4375803621988389731799033530075237868110e-21 + 0.4378257977686804492768642780897650927167 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0x5b06b680ea2ccp-52 + 0xef452b965da9fp-52 i) == 3.6079845358966994996207055940336690133424e-30 + 0.5243112258263349992771652393178033846555 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0x9b57bp-20 + 0xcb7b4p-20 i) == -1.7182001068739620267773842120965071561416e-11 + 0.3990121149225253562859800593935899629087 i":
+double: 1
idouble: 1
Test "Real part of: clog10 (0xf2p-10 + 0x3e3p-10 i) == 2.6921240173351112953324592659528481616879e-06 + 0.5785726025799636431142862788413361783862 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0xf2p-10 + 0x3e3p-10 i) == 2.6921240173351112953324592659528481616879e-06 + 0.5785726025799636431142862788413361783862 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (0xfe961079616p-45 + 0x1bc37e09e6d1p-45 i) == 2.3329549194675052736016290082882121135546e-26 + 0.4561756099441139182878993697611751382976 i":
+double: 1
idouble: 1
Test "Imaginary part of: clog10 (1.0 + 0x1.234566p-10 i) == 2.680828048441605163181684680300513080769e-7 + 4.825491868832381486767558728169977751564e-4 i":
double: 1
http://sources.redhat.com/git/gitweb.cgi?p=glibc.git;a=commitdiff;h=105ca950d968841c7b62178397505438b8e0a6ba
commit 105ca950d968841c7b62178397505438b8e0a6ba
Author: Chris Metcalf <cmetcalf@tilera.com>
Date: Sat Nov 3 08:39:40 2012 -0400
elf.h: add new tilegx relocations (copy from binutils trunk)
diff --git a/ChangeLog b/ChangeLog
index 16fa8ac..ad034366 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2012-11-02 Chris Metcalf <cmetcalf@tilera.com>
+
+ * elf/elf.h (R_TILEGX_IMM16_X[01]_HW[012]_(|LAST_)PLT_PCREL): Add.
+
2012-11-03 Andreas Schwab <schwab@linux-m68k.org>
* scripts/cross-test-ssh.sh (command): Use newlines to separate
diff --git a/elf/elf.h b/elf/elf.h
index 41fc3bd..2524924 100644
--- a/elf/elf.h
+++ b/elf/elf.h
@@ -2986,12 +2986,18 @@ typedef Elf32_Addr Elf32_Conflict;
#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */
#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */
#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */
-/* Relocs 66-71 are currently not defined. */
+#define R_TILEGX_IMM16_X0_HW0_PLT_PCREL 66 /* X0 pipe PC-rel PLT hword 0 */
+#define R_TILEGX_IMM16_X1_HW0_PLT_PCREL 67 /* X1 pipe PC-rel PLT hword 0 */
+#define R_TILEGX_IMM16_X0_HW1_PLT_PCREL 68 /* X0 pipe PC-rel PLT hword 1 */
+#define R_TILEGX_IMM16_X1_HW1_PLT_PCREL 69 /* X1 pipe PC-rel PLT hword 1 */
+#define R_TILEGX_IMM16_X0_HW2_PLT_PCREL 70 /* X0 pipe PC-rel PLT hword 2 */
+#define R_TILEGX_IMM16_X1_HW2_PLT_PCREL 71 /* X1 pipe PC-rel PLT hword 2 */
#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */
#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */
#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */
#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */
-/* Relocs 76-77 are currently not defined. */
+#define R_TILEGX_IMM16_X0_HW3_PLT_PCREL 76 /* X0 pipe PC-rel PLT hword 3 */
+#define R_TILEGX_IMM16_X1_HW3_PLT_PCREL 77 /* X1 pipe PC-rel PLT hword 3 */
#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */
#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */
#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */
@@ -3007,7 +3013,12 @@ typedef Elf32_Addr Elf32_Conflict;
/* Relocs 90-91 are currently not defined. */
#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */
#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */
-/* Relocs 94-99 are currently not defined. */
+#define R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 94 /* X0 pipe PC-rel PLT last hword 0 */
+#define R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 95 /* X1 pipe PC-rel PLT last hword 0 */
+#define R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 96 /* X0 pipe PC-rel PLT last hword 1 */
+#define R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 97 /* X1 pipe PC-rel PLT last hword 1 */
+#define R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 98 /* X0 pipe PC-rel PLT last hword 2 */
+#define R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 99 /* X1 pipe PC-rel PLT last hword 2 */
#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */
#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */
#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */
-----------------------------------------------------------------------
Summary of changes:
ChangeLog | 4 ++++
elf/elf.h | 17 ++++++++++++++---
ports/ChangeLog.tile | 4 ++++
ports/sysdeps/tile/libm-test-ulps | 16 ++++++++++++++++
4 files changed, 38 insertions(+), 3 deletions(-)
hooks/post-receive
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