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[Bug libc/6411] PowerPC: Extend fpu fenv operations to operate on 64-bit FPSCR


------- Additional Comments From rsa at us dot ibm dot com  2008-08-18 22:04 -------
(In reply to comment #7)
> Why is it necessary to have arch-dependent binaries for this?  It's really a
> single instruction.  Why not make this a dynamic decision based on the CPU in use?

Yes it is a single instruction where the new form takes an additional parameter
to indicate the length of the FPSCR to operate upon.  The content of the FPSCR
has always been loaded/stored from a double, but until ISA 2.05 the actual FPSCR
was only 32-bits.

The _ARCH_PWR6_ define is used by GCC to indicate ISA 2.05 conformance.  This
will evaluate as 'true' on a POWER7 as well, and any future architecture that is
ISA 2.05 conforming.  The 64-bit FPSCR is not an optional part of ISA 2.05.  We
don't envision another change in the FPSCR's size for quite some time since
there are 27 available reserve bits for future ISA additions.

So it seems an unnecessary burden to make a dynamic check at runtime for
something that won't change for a very long time.

> I told you before the formatting is off.  Indent the preprocessor directives.

I had two different formats of indentation going on so I'm hoping that you mean:
#ifdef FOO
# define BAR
# ifdef FAZ
#  #define BAZ
# endif
#endif

> Also, the attribution in the initial comment is
> 
>    Contributed by Name <email>.

Okay.

> Furthermore, the ChangeLog always start capitalized and with a full stop.

Yes.

> Finally, change the state from WAITING when you add a reply.

Okay, I'll document this on the wiki under bugzilla policies.

I'll have a patch ready soon.

-- 


http://sourceware.org/bugzilla/show_bug.cgi?id=6411

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