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Re: Can this be happening?
- From: Balazs Scheidler <bazsi at balabit dot hu>
- To: Daniel Jacobowitz <drow at false dot org>
- Cc: Jim Blandy <jimb at codesourcery dot com>, "Mohammed, Moqtadir" <Moqtadir_Mohammed at reyrey dot com>, gdb at sourceware dot org
- Date: Thu, 05 Jul 2007 21:26:24 +0200
- Subject: Re: Can this be happening?
- References: <D8FBABA1EF6F2E4DBCC88903F60691F30A4401F9@houxchsvr.ucscorp.ucs.pvt> <m3y7hx2mms.fsf@codesourcery.com> <20070703215751.GA941@caradoc.them.org>
On Tue, 2007-07-03 at 17:57 -0400, Daniel Jacobowitz wrote:
> On Tue, Jul 03, 2007 at 02:38:51PM -0700, Jim Blandy wrote:
> > I don't know why the upper bits would be set. GDB may be
> > misinterpreting the information in the core file.
>
> The kernel dumps it as 32-bit too. It's not clear what those bits are
> for, but I bet they're really in your core dump and you should ask the
> kernel developers.
>
> Moves from the segment registers may leave implementation defined data
> in the upper half register - but that's only for fairly old Intel
> processors.
>
IIRC the processor-defined TSS (Task State Segment) uses 32 bit values
for segment registers, although as I know TSS is not used anymore by
recent kernels.
--
Bazsi