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Re: Troubles building cris target
- From: Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>
- To: jimb at redhat dot com
- Cc: hans-peter dot nilsson at axis dot com, cgen at sourceware dot org, orjan dot friberg at axis dot com, gdb at sources dot redhat dot com
- Date: Wed, 16 Mar 2005 19:24:21 +0100
- Subject: Re: Troubles building cris target
> From: Jim Blandy <jimb@redhat.com>
> Date: 16 Mar 2005 12:53:10 -0500
> Hans-Peter Nilsson <hans-peter.nilsson@axis.com> writes:
> > JFTR, I built sim successfully on i686-pc-linux-gnu (FC2) with
> > CVS as of "Tue Mar 15 15:09:24 UTC 2005".
>
> Hm. Our systems look identical except for the processor. Do you know
> why it builds for you, but not for me?
I can only assume that inlining limits are different. (Either
we're using different GCC versions or inlining parameters for
x86_64 trig differently.)
The comment in the patch mentioned outlining of operator
functions. Without the patch, they are never outlined, so if
there's a call to the outlined function (as happened for you),
it will not be found.
> It dies differently now:
>
> gcc -DHAVE_CONFIG_H -DWITH_DEFAULT_MODEL='"crisv32"' -DPROFILE=1 -DWITH_PROFILE=-1 -DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT -DWITH_ENVIRONMENT=ALL_ENVIRONMENT -DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN -DWITH_SCACHE=16384 -I. -I/home/jimb/gdb/src/sim/cris -I../common -I/home/jimb/gdb/src/sim/cris/../common -I../../include -I/home/jimb/gdb/src/sim/cris/../../include -I../../bfd -I/home/jimb/gdb/src/sim/cris/../../bfd -I../../opcodes -I/home/jimb/gdb/src/sim/cris/../../opcodes -I../../intl -I/home/jimb/gdb/src/sim/cris/../../intl -g3 -o run \
> nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a ../../libiberty/libiberty.a -lnsl
> libsim.a(decodev10.o)(.text+0x771a): In function `crisv10f_decode':
> /home/jimb/gdb/src/sim/cris/decodev10.c:5059: undefined reference to `EXTHISI'
Ugh. Looks like I'd need to #define EXTHISI too, perhaps others.
But the obvious just dawned on me: the generated decode*.c
should have an '#include "cgen-ops.h"'. Completely untested.
CGENers, please comment.
Decoding of instruction fields should be able to use the usual
operators. Dunno if that's supposed to be handled elsewhere.
Maybe this is related to the problem generating SID CPU files
since about a year (reported before, no clue received).
Ok to commit if it works?
2005-03-16 Hans-Peter Nilsson <hp@axis.com>
* sim-decode.scm (cgen-decode.c): Include cgen-ops.h.
Index: sim-decode.scm
===================================================================
RCS file: /cvs/src/src/cgen/sim-decode.scm,v
retrieving revision 1.9
diff -c -p -r1.9 sim-decode.scm
*** sim-decode.scm 8 Jul 2003 16:19:35 -0000 1.9
--- sim-decode.scm 16 Mar 2005 18:17:07 -0000
*************** const IDESC *
*** 582,587 ****
--- 582,588 ----
#define WANT_CPU_@CPU@
#include \"sim-main.h\"
+ #include \"cgen-ops.h\"
#include \"sim-assert.h\"\n\n"
(lambda () (-gen-decode-insn-globals (non-multi-insns (non-alias-insns (current-insn-list)))))
brgds, H-P