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Re: RFC: Unpredictable register set operations
- From: Kevin Buettner <kevinb at redhat dot com>
- To: Daniel Jacobowitz <drow at mvista dot com>, gdb at sources dot redhat dot com
- Date: Tue, 15 Jul 2003 15:26:56 -0700
- Subject: Re: RFC: Unpredictable register set operations
- References: <20030715220923.GA30513@nevyn.them.org>
On Jul 15, 6:09pm, Daniel Jacobowitz wrote:
> Consider PowerPC and the $ps register (MSR). When debugging a kernel or
> embedded application, GDB has pretty complete control (?) over this
> register. In GNU/Linux userspace, however, only two bits of it can be set.
> The rest are read-only.
>
> So what happens if you "set $ps = 0"? Well, the right thing happens, but
> until the next time the target stops "print $ps" will print 0. Which is not
> actually the value of the $ps register.
>
> Here's the options that I see:
> - Ignore and document this.
> - Refetch registers after storing them.
> - Invalidate registers for lazy re-fetch after storing them.
> - Add a target hook for might-be-volatile registers, and invalidate
> only those registers after storing them - or don't cache them at
> all.
One of the refetch options (lazy or not) sounds good to me. The
target hook idea sounds like overkill, and I think we can do better
than "ignore and document".
Kevin