Re: MIPS o32 ABI spec, $fp1 valid?

[cgd at broadcom dot com]

At Mon, 16 Jun 2003 18:52:04 +0000 (UTC), "Daniel Jacobowitz" wrote:
> Co-processor 1 adds 32 32-bit floating-point general registers and a
> 32-bit control/status register. Each even/odd pair of the 32
> floating-point general registers can be used as either a 32-bit
> single-precision floating-point register or as a 64-bit
> double-precision floating-point register. For single-precision values,
> the even-numbered floating-point register holds the value. For
> double-precision values, the even-numbered floating-point register
> holds the least significant 32 bits of the value and the odd-numbered
> floating-point register holds the most significant 32 bits of the
> value. This is always true, regardless of the byte ordering conventions
> in use ( big endian or little endian).

FYI, the above agrees with my reading of Kane (see
http://sources.redhat.com/ml/gdb-patches/2003-06/msg00555.html ).

The ISBN is 0135847494.  it can be found used in lots of places for
approx $10.  I paid more for mine 10+ years ago.  8-)


> Which is actually pretty ambiguous,

not really at all: "Each even/odd pair... as either _a_ 32-bit ..."
etc.

Kane makes clear:

        In the following pages, the notation <i>FGR</i> refers to the
        FPA's general register 0 through 31, and <i>FPR</i> refers ot
        the FPA's floating-point registers (FPR 0 through 30) which
        are formed by concatenation of FGR's[sic] (as described in
        <b>Chapter 6</b>).

Chapter 6 really makes quite clear that there are 16 FGRs.



cgd