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> Having either the debug-info register numbers See my other reply. The debug-info registers do not impose order on the register cache. > or a single target impose an > order on the regcache is broken. And fixing remote.c is on the hit list (I should fix Daniel's bug) :-) It already has an internal table that does a mapping only it is 1:1. remote.c is complicated, however. The mapping will need to be defined at run (and not compile) time - this makes trying to perform transformations (and not simple mappings) on the way through more difficult. > Consider the case where we have two > target interfaces that need to mandate different orderings; clearly one of > them must fail. Similarly, having the debug-info mandate an ordering is > equally broken -- consider two ABIs which use different numbering in the > debug info. Clearly, the only way to solve this is to have mapping > layers, at least in concept, at each interface. Then the tdep code is > free to select any ordering it likes in the cache; typically an ordering > that will lead to greatest efficiency. Here, you're preaching to the converted :-) enjoy, Andrew
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