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Re: [PATCH] Look for FIR in the last FreeBSD/mips floating-point register.
- From: John Baldwin <jhb at freebsd dot org>
- To: "Maciej W. Rozycki" <macro at imgtec dot com>
- Cc: gdb-patches at sourceware dot org
- Date: Tue, 13 Jun 2017 09:37:11 -0700
- Subject: Re: [PATCH] Look for FIR in the last FreeBSD/mips floating-point register.
- Authentication-results: sourceware.org; auth=none
- References: <20170531165803.50633-1-jhb@FreeBSD.org> <1648023.dfXdf8hDrr@ralph.baldwin.cx> <alpine.DEB.2.00.1706122119360.21750@tp.orcam.me.uk>
On Monday, June 12, 2017 09:23:22 PM Maciej W. Rozycki wrote:
> On Mon, 12 Jun 2017, John Baldwin wrote:
>
> > > Well, CP1.FIR is generally expected to hold non zero; in particular in
> > > legacy MIPS processors (before CP0.Config1.FP was defined) checking for a
> > > non-zero value in CP1.FIR (bits 15:8 specifically) was the recommended way
> > > to detect the presence of FPU hardware[1]. And from MIPSr1 on there have
> > > to be floating-point formats supported reported in CP1.FIR, with D and S
> > > being mandatory, so you'll see non-zero bits at least in their positions
> > > (the W bit was only added with MIPSr2).
> >
> > Ah, I had been going off of my (probably stale) copy of See Mips Run which
> > only talks about comparing FIR with 0. FreeBSD requires MIPSr3, so it should
> > always see a non-zero FIR then.
>
> FAOD MIPSr3 (as in MIPS32r3/MIPS64r3) or MIPS III?
Sorry, MIPS III only (so now I'm not certain if a non-zero FIR is guaranteed).
The only mips bits I have worked with myself are either qemu's malta targets
and a mips4000-ish 64-bit research CPU (all of which have FPUs).
--
John Baldwin