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RE: [patch] Enable dwarf unwind for AVR target
- From: "Sivanupandi, Pitchumani" <Pitchumani dot Sivanupandi at atmel dot com>
- To: Pedro Alves <palves at redhat dot com>, "troth at openavr dot org" <troth at openavr dot org>, "brobecker at adacore dot com" <brobecker at adacore dot com>, "gdb-patches at sourceware dot org" <gdb-patches at sourceware dot org>
- Date: Tue, 5 Jan 2016 06:44:56 +0000
- Subject: RE: [patch] Enable dwarf unwind for AVR target
- Authentication-results: sourceware.org; auth=none
- References: <CAC140656783604CABA6AE60C2A6D5A4CA3B38C1 at penmbx02 dot corp dot atmel dot com> <568A7A4F dot 2060504 at redhat dot com>
> -----Original Message-----
> From: Pedro Alves [mailto:palves@redhat.com]
> Sent: 04 January 2016 19:28
> To: Sivanupandi, Pitchumani <Pitchumani.Sivanupandi@atmel.com>;
> troth@openavr.org; brobecker@adacore.com; gdb-patches@sourceware.org
> Subject: Re: [patch] Enable dwarf unwind for AVR target
>
> On 01/04/2016 08:01 AM, Sivanupandi, Pitchumani wrote:
> > - AVR_NUM_PSEUDO_REGS = 1,
> > + AVR_DWARF2_PC_REGNUM = 36 /*LR*/,
>
> It's hard to comment without some explanation for the design choices in the
> patch, and/or some understanding of what this register is.
> Seems odd that you create the register and then avr_pseudo_register_read
> already returns <unavailable>? Why did you need to add it? Is this a real
> machine register? What's LR?
>
> > + AVR_NUM_PSEUDO_REGS = 2,
> >
> > AVR_PC_REG_INDEX = 35, /* index into array of registers */
> >
> > @@ -211,7 +213,7 @@ avr_register_name (struct gdbarch *gdbarch, int
> regnum)
> > "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
> > "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
> > "SREG", "SP", "PC2",
> > - "pc"
> > + "pc", "LR"
> > };
AVR has only 32 registers. GDB maps status register, SP and PC to numbers 32,
33 and 34 respectively.
Dwarf debug info generated by avr-gcc denotes the return address by register
36 which is not an actual register.
e.g. .debug_frame
(--snip--)
00000000 00000010 ffffffff CIE
Version: 1
Augmentation: ""
Code alignment factor: 2
Data alignment factor: -1
Return address column: 36
DW_CFA_def_cfa: r32 ofs 3
DW_CFA_offset: r36 at cfa-2
(--snip--)
The fix is to add a pseudo register (36 - AVR_DWARF2_PC_REGNUM) to gdb to map
return address register in .debug_frame. Register name is "LR" (link register).
When dwarf frame unwind asks for PC, target function should find return address
value (AVR_DWARF2_PC_REGNUM).
Dwarf frame reader records all registers from the .debug_frame section.
When gdb asks for PC value to unwind, avr_dwarf2_prev_register finds the frame
address recorded for AVR_DWARF2_PC_REGNUM and read value from that memory.
(avr_dwarf2_prev_register implementation is similar to existing
avr_frame_prev_register function)
I assumed pseudo register read/write for this register not mandatory for dwarf
frame unwind. So, left it with dummy implementation as of now.
NOTE:
* Added extern function dwarf2_frame_addr to dwarf2-frame.c to find the frame
address for argument register from dwarf frame cache.
* dwarf2 address size set to 4.
Regards,
Pitchumani