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Re: [PATCH] Recognize branch instruction on MIPS in gdb.trace/entry-values.exp
- From: "Maciej W. Rozycki" <macro at codesourcery dot com>
- To: Yao Qi <yao at codesourcery dot com>
- Cc: <gdb-patches at sourceware dot org>
- Date: Tue, 30 Dec 2014 14:17:17 +0000
- Subject: Re: [PATCH] Recognize branch instruction on MIPS in gdb.trace/entry-values.exp
- Authentication-results: sourceware.org; auth=none
- References: <1419840861-10723-1-git-send-email-yao at codesourcery dot com> <alpine dot DEB dot 1 dot 10 dot 1412292255010 dot 19155 at tp dot orcam dot me dot uk> <87zja5uxjk dot fsf at codesourcery dot com>
On Tue, 30 Dec 2014, Yao Qi wrote:
> > What's the semantics of the test case and the changes you're making?
> >
>
> dwarf assembler is used to generate debug info with DW_TAG_GNU_call_site
> and DW_TAG_GNU_call_site_parameter to exercise GDB. The change I am
> making in this patch is to recognize branch instruction on MIPS, so that
> we can compute the address returned from foo, and fill it in the
> generated debug info.
Ah, OK.
> > I'm asking because the MIPS architecture has several instructions used to
> > make procedure calls, depending on the ISA and ABI selected, and also
> > compiler options. Besides JAL these instructions include JALS, JALX,
> > JALR, JALRC, JALRS, BAL and BALS. It looks to me you need to modify the
> > pattern here to take these into account; JALRC does not have a delay slot.
> >
>
> I'll update the pattern to {jalrc|(?:jal|bal)[^\r\n]+\r\n}
I think {jalrc|[jb]al[^\r\n]+\r\n} will be a little bit more efficient,
but please make sure too that the right-hand side branch does not swallow
`jalrc' with its following instruction by greedy matching:
"An RE consisting of two or more branches connected by the | operator
prefers longest match."
(from the TCL Reference Manual) -- so I think you'll have to modify your
regexp further yet.
> >> All tests in entry-values.exp are PASS.
> >
> > Which target and ABI(s) did you ran your testing on? Please try at least
> > these: o32/MIPS, o32/MIPS16, o32/microMIPS, n64 on a Linux and a
> > bare-metal target each; testing o32/MIPS16 with the `-mflip-mips16' GCC
> > option too will be appreciated. These combinations should trigger some
> > (although not all) of the other possible instructions.
>
> To avoid of misunderstanding, let me map them to the following concrete gcc
> options (I don't find -mabi=o32 nor -mabi=n64 in
> https://gcc.gnu.org/onlinedocs/gcc/MIPS-Options.html),
>
> -mabi=32
> -mabi=32 -mips16
> -mabi=32 -mips16 -mflip-mips16
> -mabi=32 -mmicromips
> -mabi=64 on both linux and bare-metal target
>
> are they what you want?
Yes, except I meant both Linux and bare-metal across all the variations,
not n64 only (missing comma after `n64' in my original sentence). Here
n64 matters as it covers PIC calling sequences.
Maciej