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Re: [PATCH v2 1/1] Documentation for MPX.
- From: Eli Zaretskii <eliz at gnu dot org>
- To: Walfred Tedeschi <walfred dot tedeschi at intel dot com>
- Cc: palves at redhat dot com, gdb-patches at sourceware dot org
- Date: Thu, 28 Nov 2013 22:12:44 +0200
- Subject: Re: [PATCH v2 1/1] Documentation for MPX.
- Authentication-results: sourceware.org; auth=none
- References: <1385636042-10592-1-git-send-email-walfred dot tedeschi at intel dot com>
- Reply-to: Eli Zaretskii <eliz at gnu dot org>
> From: Walfred Tedeschi <walfred.tedeschi@intel.com>
> Cc: gdb-patches@sourceware.org, Walfred Tedeschi <walfred.tedeschi@intel.com>
> Date: Thu, 28 Nov 2013 11:54:02 +0100
>
> I tried to cover all feedback you gave me.
> Concerning the footnote I have reduced it to avoid
> early confusion, the topic will be explained anyhow later.
Thanks.
> diff --git a/gdb/NEWS b/gdb/NEWS
> index 9fc3638..fdb33d4 100644
> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -5558,3 +5558,5 @@ GDB now handles cross debugging. If you are remotely debugging between
> two different machines, type ``./configure host -target=targ''.
> Host is the machine where GDB will run; targ is the machine
> where the program that you are debugging will run.
> +
> + * GDB now supports access to Intel(R) MPX registers on GNU/Linux.
This is OK.
> +@cindex Intel(R) Memory Protection Extensions (MPX).
> +@subsubsection Intel(R) @dfn{Memory Protection Extensions} (MPX).
@cindex should be after the @subsubsection line.
> +@item bnd0raw..bnd3raw and bnd0@dots{}bnd3 registers display.
> +Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
> +@footnote{The register named with capital letters represent the architecture
> +registers.} through @samp{BND3}. Bound registers store a pair of 64-bit values
> +which are the lower bound and upper bound. Bounds are effective addresses or
> +memory locations. The upper bounds are architecturally represented in 1's
> +complement form. A bound having lower bound = 0, and upper bound = 0
> +(1's complement of all bits set) will allow access to the entire address space.
> +
> +Architecture registers @samp{BND0} through @samp{BND3} are
> +represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.
Hmm... didn't I suggest to use "raw registers" instead of
"architectural registers"? In fact, what are the differences between
this version of the patch and the previous one, they seem identical.