[patch] sim: bfin: handle invalid HLs encoding in dsp shift insns

[Mike Frysinger <vapier at gentoo dot org>]

For many of the 32bit dsp shift related insns, we were just ignoring the HLs
field.  The hardware does not though and will reject the insn if it's set
incorrectly.  Update the sim to match.

Committed.
-mike

2013-06-23  Mike Frysinger  <vapier@gentoo.org>

    * bfin-sim.c (decode_dsp32shift_0): Make sure HLs is 0 after last
    insn that uses it.
    (decode_dsp32shiftimm_0): Likewise.
    Require HLs be less than 2 for accumulator shift insns.

--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -5378,6 +5378,9 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       STORE (AWREG (HLs), (val & 0xffffffff));
       STORE (ASTATREG (av[HLs]), 0);
     }
+  else if (HLs != 0)
+    /* All the insns after this point don't use HLs.  */
+    illegal_instruction (cpu);
   else if ((sop == 0 || sop == 1) && sopcde == 1 && HLs == 0)
     {
       bs32 shft = (bs8)(DREG (src0) << 2) >> 2;
@@ -5962,12 +5965,11 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       if (shift)
 	SET_CCREG (cc);
     }
-  else if (sop == 0 && sopcde == 3 && bit8 == 1)
+  else if (sop == 0 && sopcde == 3 && bit8 == 1 && HLs < 2)
     {
       /* Arithmetic shift, so shift in sign bit copies.  */
       bu64 acc, val;
       int shift = uimm5 (newimmag);
-      HLs = !!HLs;
 
       TRACE_INSN (cpu, "A%i = A%i >>> %i;", HLs, HLs, shift);
 
@@ -5983,13 +5985,12 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       STORE (ASTATREG (az), !val);
       STORE (ASTATREG (av[HLs]), 0);
     }
-  else if ((sop == 0 && sopcde == 3 && bit8 == 0)
-	   || (sop == 1 && sopcde == 3))
+  else if (((sop == 0 && sopcde == 3 && bit8 == 0)
+	   || (sop == 1 && sopcde == 3)) && HLs < 2)
     {
       bu64 acc;
       int shiftup = uimm5 (immag);
       int shiftdn = uimm5 (newimmag);
-      HLs = !!HLs;
 
       TRACE_INSN (cpu, "A%i = A%i %s %i;", HLs, HLs,
 		  sop == 0 ? "<<" : ">>",
@@ -6016,6 +6017,9 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       SET_ASTATREG (an, !!(acc & 0x8000000000ull));
       SET_ASTATREG (az, (acc & 0xFFFFFFFFFF) == 0);
     }
+  else if (HLs != 0)
+    /* All the insns after this point don't use HLs.  */
+    illegal_instruction (cpu);
   else if (sop == 1 && sopcde == 1 && bit8 == 0)
     {
       int count = imm5 (immag);

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