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Re: FAIL: v850 divh.cgs (Re: [v850 sim] Fix div, shift, sat, bsh opcodes, add initial testsuite)
> Perhaps the code isn't 64-bit-clean?
I think, in general, the v850 sim won't be 64-bit clean, but I did at
least clean up the opcodes we're testing so far.
* simops.c (OP_1C007E0): Compensate for 64 bit hosts.
(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
Index: simops.c
===================================================================
RCS file: /cvs/src/src/sim/v850/simops.c,v
retrieving revision 1.9
diff -p -U3 -r1.9 simops.c
--- simops.c 6 Feb 2008 00:40:05 -0000 1.9
+++ simops.c 6 Feb 2008 04:38:31 -0000
@@ -2209,8 +2209,8 @@ OP_1C007E0 (void)
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
- divide_by = State.regs[ OP[0] ];
- divide_this = State.regs[ OP[1] ] << imm5;
+ divide_by = (signed32) State.regs[ OP[0] ];
+ divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@@ -2280,7 +2280,7 @@ OP_18007E0 (void)
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
divide_by = EXTEND16 (State.regs[ OP[0] ]);
- divide_this = State.regs[ OP[1] ] << imm5;
+ divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
@@ -2351,14 +2351,14 @@ OP_2C007E0 (void)
/* Compute the result. */
- divide_by = State.regs[ OP[0] ];
+ divide_by = (signed32) State.regs[ OP[0] ];
divide_this = State.regs[ OP[1] ];
if (divide_by == 0)
{
PSW |= PSW_OV;
}
- else if (divide_by == -1 && divide_this == (1 << 31))
+ else if (divide_by == -1 && divide_this == (1L << 31))
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@@ -2367,9 +2367,10 @@ OP_2C007E0 (void)
}
else
{
+ divide_this = (signed32) divide_this;
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
-
+
/* Set condition codes. */
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
@@ -2442,7 +2443,7 @@ OP_28007E0 (void)
{
PSW |= PSW_OV;
}
- else if (divide_by == -1 && divide_this == (1 << 31))
+ else if (divide_by == -1 && divide_this == (1L << 31))
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@@ -2451,6 +2452,7 @@ OP_28007E0 (void)
}
else
{
+ divide_this = (signed32) divide_this;
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
Index: v850.igen
===================================================================
RCS file: /cvs/src/src/sim/v850/v850.igen,v
retrieving revision 1.8
diff -p -U3 -r1.8 v850.igen
--- v850.igen 6 Feb 2008 00:40:05 -0000 1.8
+++ v850.igen 6 Feb 2008 04:38:31 -0000
@@ -356,7 +356,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
op0 = EXTEND16 (State.regs[OP[0]]);
op1 = State.regs[OP[1]];
- if (op0 == 0xffffffff && op1 == 0x80000000)
+ if (op0 == -1 && op1 == 0x80000000)
{
PSW &= ~PSW_Z;
PSW |= PSW_OV | PSW_S;
@@ -368,7 +368,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
}
else
{
- result = op1 / op0;
+ result = (signed32) op1 / op0;
ov = 0;
/* Compute the condition codes. */