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CGEN simulators now brokenly require CGEN disassemblers...
- From: Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>
- To: binutils at sourceware dot org, gdb-patches at sourceware dot org
- Cc: brolley at redhat dot com
- Date: Fri, 2 Dec 2005 05:02:13 +0100
- Subject: CGEN simulators now brokenly require CGEN disassemblers...
I'd prefer not to commit this, but instead break out the CGEN
bitset operators into a separate file, say, cgen-bitops.c. (I
think that would arguably be covered by the "obvious" rule, but
solicit feedback anyway). As a stopgap I need like the
following to build a re-generated CRIS sim (once the CGEN
breakage is fixed; see recent post there), as simulators now
refer to some new bitset operators defined in
opcodes/cgen-opc.c. For CRIS, only the simulator is
CGEN-generated; the disassembler and everything else is
"manual".
opcodes/:
* configure.in <bfd_cris_arch>: Add cgen-opc.lo.
* configure: Regenerate.
sim/:
* cris/sim-if.c (cgen_dis_lookup_insn): Stub function.
Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.64
diff -p -u -r1.64 configure.in
--- opcodes/configure.in 25 Oct 2005 17:40:16 -0000 1.64
+++ opcodes/configure.in 2 Dec 2005 03:48:12 -0000
@@ -158,7 +158,8 @@ if test x${all_targets} = xfalse ; then
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
- bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo" ;;
+ # The file cgen-opc.lo is only needed for the simulator.
+ bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-opc.lo" ;;
bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;;
bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;;
bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;;
Index: sim/cris/sim-if.c
===================================================================
RCS file: /cvs/src/src/sim/cris/sim-if.c,v
retrieving revision 1.1
diff -p -u -r1.1 sim-if.c
--- sim/cris/sim-if.c 28 Jan 2005 04:29:00 -0000 1.1
+++ sim/cris/sim-if.c 2 Dec 2005 03:48:20 -0000
@@ -588,3 +588,15 @@ cris_disassemble_insn (SIM_CPU *cpu,
pinsn = cris_get_disassembler (STATE_PROG_BFD (sd));
(*pinsn) (pc, &disasm_info);
}
+
+/* Central bits of the simulator need functions in opcodes/cgen-opc.c,
+ which in turn refers to cgen_dis_lookup_insn, but we'll never call
+ the caller, as we have a non-CGEN disassembler. This is a kludge
+ until the bitset functions of cgen-opc.c are broken out of the
+ cgen-disassembler. */
+
+CGEN_INSN_LIST *
+cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value)
+{
+ abort ();
+}
brgds, H-P