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Update ARM sim to handle some Thumbv2 instructions


Hi Guys,

  I am applying the patch below to update the ARM simulator so that it
  can handle some THUMBv2 instructions, specifically those that can
  now be generated by gcc when it is running in ARMv6 and THUMB mode.

Cheers
  Nick

sim/arm/ChangeLog
2005-05-24  Nick Clifton  <nickc@redhat.com>

	* thumbemu.c (handle_v6_thumb_insn): New function.
	(ARMul_ThumbDecode): Call handle_v6_thumb_insn() when an undefined
	instruction binary is encountered.

Index: sim/arm/thumbemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/thumbemu.c,v
retrieving revision 1.6
diff -c -3 -p -r1.6 thumbemu.c
*** sim/arm/thumbemu.c	12 May 2005 07:36:59 -0000	1.6
--- sim/arm/thumbemu.c	24 May 2005 15:28:30 -0000
*************** existing ARM simulator.  */
*** 31,50 ****
  #include "armemu.h"
  #include "armos.h"
  
  /* Decode a 16bit Thumb instruction.  The instruction is in the low
     16-bits of the tinstr field, with the following Thumb instruction
     held in the high 16-bits.  Passing in two Thumb instructions allows
     easier simulation of the special dual BL instruction.  */
  
! tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
!      ARMul_State *
!        state;
!      ARMword
!        pc;
!      ARMword
!        tinstr;
!      ARMword *
!        ainstr;
  {
    tdstate valid = t_decoded;	/* default assumes a valid instruction */
    ARMword next_instr;
--- 31,104 ----
  #include "armemu.h"
  #include "armos.h"
  
+ /* Attempt to emulate an ARMv6 instruction.
+    Stores t_branch into PVALUE upon success or t_undefined otherwise.  */
+ 
+ static void
+ handle_v6_thumb_insn (ARMul_State * state,
+ 		      ARMword       tinstr,
+ 		      tdstate *     pvalid)
+ {
+   ARMword Rd;
+   ARMword Rm;
+ 
+   if (! state->is_v6)
+     {
+       * pvalid = t_undefined;
+       return;
+     }
+ 
+   switch (tinstr & 0xFFC0)
+     {
+     case 0xb660: /* cpsie */
+     case 0xb670: /* cpsid */
+     case 0x4600: /* cpy */
+     case 0xba00: /* rev */
+     case 0xba40: /* rev16 */
+     case 0xbac0: /* revsh */
+     case 0xb650: /* setend */
+     default:  
+       printf ("Unhandled v6 thumb insn: %04x\n", tinstr);
+       * pvalid = t_undefined;
+       return;
+ 
+     case 0xb200: /* sxth */
+       Rm = state->Reg [(tinstr & 0x38) >> 3];
+       if (Rm & 0x8000)
+ 	state->Reg [(tinstr & 0x7)] = (Rm & 0xffff) | 0xffff0000;
+       else
+ 	state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
+       break;
+     case 0xb240: /* sxtb */
+       Rm = state->Reg [(tinstr & 0x38) >> 3];
+       if (Rm & 0x80)
+ 	state->Reg [(tinstr & 0x7)] = (Rm & 0xff) | 0xffffff00;
+       else
+ 	state->Reg [(tinstr & 0x7)] = Rm & 0xff;
+       break;
+     case 0xb280: /* uxth */
+       Rm = state->Reg [(tinstr & 0x38) >> 3];
+       state->Reg [(tinstr & 0x7)] = Rm & 0xffff;
+       break;
+     case 0xb2c0: /* uxtb */
+       Rm = state->Reg [(tinstr & 0x38) >> 3];
+       state->Reg [(tinstr & 0x7)] = Rm & 0xff;
+       break;
+     }
+   /* Indicate that the instruction has been processed.  */
+   * pvalid = t_branch;
+ }
+ 
  /* Decode a 16bit Thumb instruction.  The instruction is in the low
     16-bits of the tinstr field, with the following Thumb instruction
     held in the high 16-bits.  Passing in two Thumb instructions allows
     easier simulation of the special dual BL instruction.  */
  
! tdstate
! ARMul_ThumbDecode (ARMul_State * state,
! 		   ARMword       pc,
! 		   ARMword       tinstr,
! 		   ARMword *     ainstr)
  {
    tdstate valid = t_decoded;	/* default assumes a valid instruction */
    ARMword next_instr;
*************** tdstate ARMul_ThumbDecode (state, pc, ti
*** 222,228 ****
  	    case 0x0:		/* UNDEFINED */
  	    case 0x4:		/* UNDEFINED */
  	    case 0x8:		/* UNDEFINED */
! 	      valid = t_undefined;
  	      break;
  	    }
  	}
--- 276,282 ----
  	    case 0x0:		/* UNDEFINED */
  	    case 0x4:		/* UNDEFINED */
  	    case 0x8:		/* UNDEFINED */
! 	      handle_v6_thumb_insn (state, tinstr, & valid);
  	      break;
  	    }
  	}
*************** tdstate ARMul_ThumbDecode (state, pc, ti
*** 370,376 ****
  	  /* Drop through.  */
  	default:
  	  /* Everything else is an undefined instruction.  */
! 	  valid = t_undefined;
  	  break;
  	}
        break;
--- 424,430 ----
  	  /* Drop through.  */
  	default:
  	  /* Everything else is an undefined instruction.  */
! 	  handle_v6_thumb_insn (state, tinstr, & valid);
  	  break;
  	}
        break;
*************** tdstate ARMul_ThumbDecode (state, pc, ti
*** 460,467 ****
  	    }
  	  valid = t_branch;
  	}
!       else			/* UNDEFINED : cc=1110(AL) uses different format */
! 	valid = t_undefined;
        break;
      case 28:			/* B */
        /* Format 18 */
--- 514,522 ----
  	    }
  	  valid = t_branch;
  	}
!       else
! 	/* UNDEFINED : cc=1110(AL) uses different format.  */
! 	handle_v6_thumb_insn (state, tinstr, & valid);
        break;
      case 28:			/* B */
        /* Format 18 */
*************** tdstate ARMul_ThumbDecode (state, pc, ti
*** 476,482 ****
  	{
  	  if (tinstr & 1)
  	    {
! 	      valid = t_undefined;
  	      break;
  	    }
  	  /* Drop through.  */
--- 531,537 ----
  	{
  	  if (tinstr & 1)
  	    {
! 	      handle_v6_thumb_insn (state, tinstr, & valid);
  	      break;
  	    }
  	  /* Drop through.  */
*************** tdstate ARMul_ThumbDecode (state, pc, ti
*** 499,506 ****
  	    break;
  	  }
  	}
!       valid = t_undefined;
        break;
      case 30:			/* BL instruction 1 */
        /* Format 19 */
        /* There is no single ARM instruction equivalent for this Thumb
--- 554,563 ----
  	    break;
  	  }
  	}
! 
!       handle_v6_thumb_insn (state, tinstr, & valid);
        break;
+ 
      case 30:			/* BL instruction 1 */
        /* Format 19 */
        /* There is no single ARM instruction equivalent for this Thumb


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