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[PATCH] some new sh-sim tests
- From: Michael Snyder <msnyder at redhat dot com>
- To: Joern Rennecke <amylaar at fairadsl dot co dot uk>, joern dot rennecke at superh dot com, gdb-patches at sources dot redhat dot com
- Date: Thu, 12 Feb 2004 14:31:51 -0800
- Subject: [PATCH] some new sh-sim tests
- Organization: Red Hat, Inc.
Committed.
Index: allinsn.exp
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/sh/allinsn.exp,v
retrieving revision 1.4
diff -p -r1.4 allinsn.exp
*** allinsn.exp 9 Jan 2004 19:47:36 -0000 1.4
--- allinsn.exp 12 Feb 2004 22:29:00 -0000
*************** set all "sh shdsp"
*** 4,9 ****
--- 4,10 ----
if [istarget sh-*elf] {
run_sim_test add.s $all
+ run_sim_test and.s $all
run_sim_test dmxy.s shdsp
run_sim_test fabs.s sh
run_sim_test fadd.s sh
*************** if [istarget sh-*elf] {
*** 31,36 ****
--- 32,38 ----
run_sim_test loop.s shdsp
run_sim_test macl.s sh
run_sim_test macw.s sh
+ run_sim_test movi.s $all
run_sim_test movli.s $all
run_sim_test movua.s $all
run_sim_test movxy.s shdsp
*************** if [istarget sh-*elf] {
*** 50,55 ****
--- 52,58 ----
run_sim_test pshlr.s shdsp
run_sim_test psub.s shdsp
run_sim_test pswap.s shdsp
+ run_sim_test sett.s $all
run_sim_test shll.s $all
run_sim_test shll2.s $all
run_sim_test shll8.s $all
Index: testutils.inc
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/sh/testutils.inc,v
retrieving revision 1.2
diff -p -r1.2 testutils.inc
*** testutils.inc 9 Jan 2004 19:47:36 -0000 1.2
--- testutils.inc 12 Feb 2004 22:29:00 -0000
*************** set_greg\@:
*** 485,493 ****
bra .Lsrbit\@
nop
.align 2
! .Lsrbitval:
.long \val
! .Lsrbit:
.endm
.macro test_sr_bit_set val
--- 485,493 ----
bra .Lsrbit\@
nop
.align 2
! .Lsrbitval\@:
.long \val
! .Lsrbit\@:
.endm
.macro test_sr_bit_set val
*************** set_greg\@:
*** 559,565 ****
.macro set_creg val reg
! #
push r0
mov.l .Lscrval\@, r0
ldc r0, \reg
--- 559,565 ----
.macro set_creg val reg
! # [gbr, vbr, ssr, spc, sgr, dbr... ]
push r0
mov.l .Lscrval\@, r0
ldc r0, \reg
Index: and.s
===================================================================
RCS file: and.s
diff -N and.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- and.s 12 Feb 2004 22:29:00 -0000
***************
*** 0 ****
--- 1,89 ----
+ # sh testcase for and
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ .align 2
+ _x: .long 0xa5a5a5a5
+ _y: .long 0x55555555
+
+ start
+
+ and_reg_reg_direct:
+ set_grs_a5a5
+ mov.l i, r1
+ mov.l j, r2
+ and r1, r2
+ test_gr0_a5a5
+ assertreg 0xa5a5a5a5 r1
+ assertreg 0xa0a0a0a0 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+ bra and_imm_reg
+ nop
+
+ .align 2
+ i: .long 0xa5a5a5a5
+ j: .long 0xaaaaaaaa
+
+ and_imm_reg:
+ set_grs_a5a5
+ and #0xff, r0
+ assertreg 0xa5, r0
+ test_gr_a5a5 r1
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ and_b_imm_ind:
+ set_grs_a5a5
+ mov.l x, r0
+ and.b #0x55, @(r0, GBR)
+ mov.l @r0, r0
+
+ assertreg 0xa5a5a505, r0
+ test_gr_a5a5 r1
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ pass
+
+ exit 0
+
+ .align 2
+ x: .long _x
+ y: .long _y
+
Index: movi.s
===================================================================
RCS file: movi.s
diff -N movi.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- movi.s 12 Feb 2004 22:29:00 -0000
***************
*** 0 ****
--- 1,35 ----
+ # sh testcase for mov <#imm>
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+
+ mov_i_reg: # Test <imm8>
+ set_grs_a5a5
+ mov #-0x55, r1
+
+ assertreg 0xffffffab, r1
+
+ test_gr_a5a5 r0
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ pass
+
+ exit 0
+
+
Index: sett.s
===================================================================
RCS file: sett.s
diff -N sett.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- sett.s 12 Feb 2004 22:29:00 -0000
***************
*** 0 ****
--- 1,65 ----
+ # sh testcase for sett, clrt, movt
+ # mach: all
+ # as(sh): -defsym sim_cpu=0
+ # as(shdsp): -defsym sim_cpu=1 -dsp
+
+ .include "testutils.inc"
+
+ start
+ sett_1: set_grs_a5a5
+ sett
+ bt .Lsett
+ nop
+ fail
+ .Lsett:
+ test_grs_a5a5
+
+ clrt_1: set_grs_a5a5
+ clrt
+ bf .Lclrt
+ nop
+ fail
+ .Lclrt:
+ test_grs_a5a5
+
+ movt_1: set_grs_a5a5
+ sett
+ movt r1
+ test_gr_a5a5 r0
+ assertreg 1, r1
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ movt_2: set_grs_a5a5
+ clrt
+ movt r1
+ test_gr_a5a5 r0
+ assertreg 0, r1
+ test_gr_a5a5 r2
+ test_gr_a5a5 r3
+ test_gr_a5a5 r4
+ test_gr_a5a5 r5
+ test_gr_a5a5 r6
+ test_gr_a5a5 r7
+ test_gr_a5a5 r8
+ test_gr_a5a5 r9
+ test_gr_a5a5 r10
+ test_gr_a5a5 r11
+ test_gr_a5a5 r12
+ test_gr_a5a5 r13
+ test_gr_a5a5 r14
+
+ pass
+
+ exit 0