This is the mail archive of the gdb-patches@sources.redhat.com mailing list for the GDB project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [RFA] Rewrite mips_get_saved_register()


This patch depends on the following (as of yet) unapproved patches:

    http://sources.redhat.com/ml/gdb-patches/2002-08/msg00189.html
    http://sources.redhat.com/ml/gdb-patches/2002-08/msg00195.html
    http://sources.redhat.com/ml/gdb-patches/2002-08/msg00196.html

Okay to commit?

	* mips-tdep.c (mips_get_saved_register): Rewrite to use
	frame_register_unwind() instead of find_saved_register().
Sorry, not like this. Can you please, for the moment, just in-line the call to find_saved_register().

(The two other bugs you fixed were definitly needed and thanks for finding them. How the code got away with not setting the SP I don't know.)

- if (raw_buffer != NULL)
- {
- LONGEST val;
- if (regnum < 32)
- /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
- saved. */
- val = read_memory_integer (addr, MIPS_SAVED_REGSIZE);
- else
- val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum));
- store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val);
- }

In theory (and emphasis on the theory) things need to be changed so that:

- 32 32 bit nameless pseudo-registers are added to the cooked register space
- the 32 64 bit gprs get given a 64 bit virtual type so that they have identical raw and virtual sizes
- The debug info, for a 32 bit ABI, maps the gpr register numbers onto the 32 bit pseudo register range
- The gdbarch pseudo register read/write function maps the 32 bit pseudo-registers onto the 64 bit gprs.
- For init saved regs, dependant on the size of the register saved, either the the address of the 64 bit GPR or the address of the 32 bit pseudo-register is set
- a custom mips register unwind function maps the requested register (64 bit gpr or 32 bit pseudo) onto: the 32 bit pseudo, the 64 bit gpr, or a further recursive unwind call. If it has to do a 32/64 mapping then it sets not-an-lval.
- you find you have to yank all sorts of register converible code

But like I said, it is theory, the mips suffers from one hack (like the above) piled on top of another (the register convertable stuff, the register raw/virtual size being different, ...). I don't know if now is the time to be experimenting with theories :-)

Andrew



Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]