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[patch] ARMulator XScale coprocessor extensions
- To: gdb-patches at sources dot redhat dot com
- subject: [patch] ARMulator XScale coprocessor extensions
- From: matthew green <mrg at cygnus dot com>
- Date: Fri, 12 Jan 2001 11:12:48 +1100
- organisation: Red Hat, Inc.
hi,
this patch adds support for several of of the xscale coprocessor registers:
- endianness bit support
- set the FSR & FAR for relevant aborts
- clock timer/counter support
- data & instruction breakpoint support
- sets the MOE (method of entry) for debugging
- model FIQ & IRQ enable bits
2001-01-04 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Pass in ARMul_State so we can set
CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
Index: armcopro.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armcopro.c,v
retrieving revision 1.4
diff -p -r1.4 armcopro.c
*** armcopro.c 2000/11/30 01:55:12 1.4
--- armcopro.c 2001/01/10 05:18:20
***************
*** 16,21 ****
--- 16,22 ----
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "armdefs.h"
+ #include "armos.h"
#include "armemu.h"
#include "ansidecl.h"
*************** check_cp15_access (ARMul_State * state,
*** 211,217 ****
/* Store a value into one of coprocessor 15's registers. */
void
! write_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm, ARMword value)
{
if (opcode_2)
{
--- 212,218 ----
/* Store a value into one of coprocessor 15's registers. */
void
! write_cp15_reg (ARMul_State * state, unsigned reg, unsigned opcode_2, unsigned CRm, ARMword value)
{
if (opcode_2)
{
*************** write_cp15_reg (unsigned reg, unsigned o
*** 245,250 ****
--- 246,260 ----
BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */
value &= 0x00003b87;
value |= 0x00000078;
+
+ /* Change the endianness if necessary */
+ if ((value & ARMul_CP15_R1_ENDIAN) !=
+ (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN))
+ {
+ state->bigendSig = value & ARMul_CP15_R1_ENDIAN;
+ /* Force ARMulator to notice these now. */
+ state->Emulate = CHANGEMODE;
+ }
break;
case 2: /* Translation Table Base. */
*************** write_cp15_reg (unsigned reg, unsigned o
*** 324,332 ****
return;
}
! /* Return the value in a cp13 register. */
! static ARMword
read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm)
{
if (opcode_2 == 0)
--- 334,342 ----
return;
}
! /* Return the value in a cp15 register. */
! ARMword
read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm)
{
if (opcode_2 == 0)
*************** XScale_cp15_LDC (ARMul_State * state, un
*** 364,370 ****
result = check_cp15_access (state, reg, 0, 0, 0);
if (result == ARMul_DONE && type == ARMul_DATA)
! write_cp15_reg (reg, 0, 0, data);
return result;
}
--- 374,380 ----
result = check_cp15_access (state, reg, 0, 0, 0);
if (result == ARMul_DONE && type == ARMul_DATA)
! write_cp15_reg (state, reg, 0, 0, data);
return result;
}
*************** XScale_cp15_MCR (ARMul_State * state,
*** 416,422 ****
result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
if (result == ARMul_DONE)
! write_cp15_reg (reg, opcode_2, CRm, value);
return result;
}
--- 426,432 ----
result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
if (result == ARMul_DONE)
! write_cp15_reg (state, reg, opcode_2, CRm, value);
return result;
}
*************** XScale_cp15_write_reg (ARMul_State * sta
*** 440,450 ****
{
/* FIXME: Not sure what to do about the alternative register set
here. For now default to just accessing CRm == 0 registers. */
! write_cp15_reg (reg, 0, 0, value);
return TRUE;
}
/* Coprocessor 13: Interrupt Controller and Bus Controller. */
/* There are two sets of registers for copro 13.
--- 450,557 ----
{
/* FIXME: Not sure what to do about the alternative register set
here. For now default to just accessing CRm == 0 registers. */
! write_cp15_reg (state, reg, 0, 0, value);
return TRUE;
}
+ /***************************************************************************\
+ * Check for special XScale memory access features *
+ \***************************************************************************/
+ void
+ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
+ {
+ ARMword dbcon, r0, r1;
+ int e1, e0;
+
+ if (!state->is_XScale)
+ return;
+
+ /* Check for PID-ification.
+ XXX BTB access support will require this test failing. */
+ r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000);
+ if (r0 && (*address & 0xfe000000) == 0)
+ *address |= r0;
+
+ /* Check alignment fault enable/disable. */
+ if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (*address & 3))
+ ARMul_Abort (state, ARMul_DataAbortV);
+
+ if (XScale_debug_moe (state, -1))
+ return;
+
+ /* Check the data breakpoint registers. */
+ dbcon = read_cp15_reg (14, 0, 4);
+ r0 = read_cp15_reg (14, 0, 0);
+ r1 = read_cp15_reg (14, 0, 3);
+ e0 = dbcon & ARMul_CP15_DBCON_E0;
+
+ if (dbcon & ARMul_CP15_DBCON_M)
+ {
+ /* r1 is a inverse mask. */
+ if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
+ && ((*address & ~r1) == (r0 & ~r1)))
+ {
+ XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
+ ARMul_OSHandleSWI (state, SWI_Breakpoint);
+ }
+ }
+ else
+ {
+ if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
+ && ((*address & ~3) == (r0 & ~3)))
+ {
+ XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
+ ARMul_OSHandleSWI (state, SWI_Breakpoint);
+ }
+
+ e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2;
+ if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1))
+ && ((*address & ~3) == (r1 & ~3)))
+ {
+ XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
+ ARMul_OSHandleSWI (state, SWI_Breakpoint);
+ }
+ }
+ }
+
+ /***************************************************************************\
+ * Check set
+ \***************************************************************************/
+ void
+ XScale_set_fsr_far(ARMul_State * state, ARMword fsr, ARMword far)
+ {
+ if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
+ return;
+
+ write_cp15_reg (state, 5, 0, 0, fsr);
+ write_cp15_reg (state, 6, 0, 0, far);
+ }
+
+ /* Set the XScale debug `method of entry' if it is enabled. */
+ int
+ XScale_debug_moe (ARMul_State * state, int moe)
+ {
+ ARMword value;
+
+ if (!state->is_XScale)
+ return 1;
+
+ value = read_cp14_reg (10);
+ if (value & (1UL << 31))
+ {
+ if (moe != -1)
+ {
+ value &= ~0x1c;
+ value |= moe;
+
+ write_cp14_reg (10, value);
+ }
+ return 1;
+ }
+ return 0;
+ }
+
/* Coprocessor 13: Interrupt Controller and Bus Controller. */
/* There are two sets of registers for copro 13.
*************** write_cp14_reg (unsigned reg, ARMword va
*** 734,739 ****
--- 841,850 ----
case 0: /* PMNC */
/* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */
value &= 0x0ffff77f;
+
+ /* Reset the clock counter if necessary */
+ if (value & ARMul_CP14_R0_CLKRST)
+ XScale_cp14_Regs [1] = 0;
break;
case 4:
Index: armdefs.h
===================================================================
RCS file: /cvs/src/src/sim/arm/armdefs.h,v
retrieving revision 1.7
diff -p -r1.7 armdefs.h
*** armdefs.h 2000/11/30 01:55:12 1.7
--- armdefs.h 2001/01/10 05:18:21
*************** struct ARMul_State
*** 102,107 ****
--- 102,110 ----
ARMul_CPWrites *CPWrite[16]; /* Write CP register */
unsigned char *CPData[16]; /* Coprocessor data */
unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
+ unsigned long LastTime; /* Value of last call to ARMul_Time() */
+ ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit
+ 3 set */
unsigned EventSet; /* the number of events in the queue */
unsigned long Now; /* time to the nearest cycle */
*************** extern ARMword ARMul_MemAccess (ARMul_St
*** 339,344 ****
--- 342,373 ----
#define ARMul_CANT 1
#define ARMul_INC 3
+ #define ARMul_CP13_R0_FIQ 0x1
+ #define ARMul_CP13_R0_IRQ 0x2
+ #define ARMul_CP13_R8_PMUS 0x1
+
+ #define ARMul_CP14_R0_ENABLE 0x0001
+ #define ARMul_CP14_R0_CLKRST 0x0004
+ #define ARMul_CP14_R0_CCD 0x0008
+ #define ARMul_CP14_R0_INTEN0 0x0010
+ #define ARMul_CP14_R0_INTEN1 0x0020
+ #define ARMul_CP14_R0_INTEN2 0x0040
+ #define ARMul_CP14_R0_FLAG0 0x0100
+ #define ARMul_CP14_R0_FLAG1 0x0200
+ #define ARMul_CP14_R0_FLAG2 0x0400
+ #define ARMul_CP14_R10_MOE_IB 0x0004
+ #define ARMul_CP14_R10_MOE_DB 0x0008
+ #define ARMul_CP14_R10_MOE_BT 0x000c
+ #define ARMul_CP15_R1_ENDIAN 0x0080
+ #define ARMul_CP15_R1_ALIGN 0x0002
+ #define ARMul_CP15_R5_X 0x0400
+ #define ARMul_CP15_R5_ST_ALIGN 0x0001
+ #define ARMul_CP15_R5_IMPRE 0x0406
+ #define ARMul_CP15_R5_MMU_EXCPT 0x0400
+ #define ARMul_CP15_DBCON_M 0x0100
+ #define ARMul_CP15_DBCON_E1 0x000c
+ #define ARMul_CP15_DBCON_E0 0x0003
+
extern unsigned ARMul_CoProInit (ARMul_State * state);
extern void ARMul_CoProExit (ARMul_State * state);
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
*************** extern void ARMul_CoProAttach (ARMul_Sta
*** 348,353 ****
--- 377,386 ----
ARMul_CDPs * cdp,
ARMul_CPReads * read, ARMul_CPWrites * write);
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
+ extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
+ int store);
+ extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
+ extern int XScale_debug_moe (ARMul_State * state, int moe);
/***************************************************************************\
* Definitons of things in the host environment *
Index: armemu.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.c,v
retrieving revision 1.17
diff -p -r1.17 armemu.c
*** armemu.c 2000/12/19 00:58:04 1.17
--- armemu.c 2001/01/10 05:18:29
*************** extern int stop_simulator;
*** 279,293 ****
are being executed: */
ARMword isize;
- #ifdef MODE32
ARMword
ARMul_Emulate32 (register ARMul_State * state)
- {
#else
- ARMword
ARMul_Emulate26 (register ARMul_State * state)
- {
#endif
register ARMword instr, /* the current instruction */
dest = 0, /* almost the DestBus */
temp, /* ubiquitous third hand */
--- 279,291 ----
are being executed: */
ARMword isize;
ARMword
+ #ifdef MODE32
ARMul_Emulate32 (register ARMul_State * state)
#else
ARMul_Emulate26 (register ARMul_State * state)
#endif
+ {
register ARMword instr, /* the current instruction */
dest = 0, /* almost the DestBus */
temp, /* ubiquitous third hand */
*************** ARMul_Emulate26 (register ARMul_State *
*** 531,536 ****
--- 529,607 ----
break;
} /* cc check */
+ /* Handle the Clock counter here. */
+ if (state->is_XScale)
+ {
+ ARMword cp14r0 = state->CPRead[14] (state, 0, 0);
+
+ if (cp14r0 && ARMul_CP14_R0_ENABLE)
+ {
+ unsigned long newcycles, nowtime = ARMul_Time(state);
+
+ newcycles = nowtime - state->LastTime;
+ state->LastTime = nowtime;
+ if (cp14r0 && ARMul_CP14_R0_CCD)
+ {
+ if (state->CP14R0_CCD == -1)
+ state->CP14R0_CCD = newcycles;
+ else
+ state->CP14R0_CCD += newcycles;
+ if (state->CP14R0_CCD >= 64)
+ {
+ newcycles = 0;
+ while (state->CP14R0_CCD >= 64)
+ state->CP14R0_CCD -= 64, newcycles++;
+ goto check_PMUintr;
+ }
+ }
+ else
+ {
+ ARMword cp14r1;
+ int do_int = 0;
+
+ state->CP14R0_CCD = -1;
+ check_PMUintr:
+ cp14r0 |= ARMul_CP14_R0_FLAG2;
+ (void) state->CPWrite[14] (state, 0, cp14r0);
+
+ cp14r1 = state->CPRead[14] (state, 1, 0);
+
+ /* coded like this for portability */
+ while (newcycles)
+ {
+ if (cp14r1 == 0xffffffff)
+ {
+ cp14r1 = 0;
+ do_int = 1;
+ }
+ else
+ cp14r1++;
+ newcycles--;
+ }
+ (void) state->CPWrite[14] (state, 1, cp14r1);
+ if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2))
+ {
+ if (state->CPRead[13] (state, 8, 0)
+ && ARMul_CP13_R8_PMUS)
+ ARMul_Abort (state, ARMul_FIQV);
+ else
+ ARMul_Abort (state, ARMul_IRQV);
+ }
+ }
+ }
+ }
+
+ /* Handle hardware instructions breakpoints here. */
+ if (state->is_XScale)
+ {
+ if ((pc | 3) == (read_cp15_reg (14, 0, 8) | 2)
+ || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2))
+ {
+ if (XScale_debug_moe (state, ARMul_CP14_R10_MOE_IB))
+ ARMul_OSHandleSWI (state, SWI_Breakpoint);
+ }
+ }
+
/***************************************************************************\
* Actual execution of instructions begins here *
\***************************************************************************/
*************** ARMul_Emulate26 (register ARMul_State *
*** 1356,1382 ****
if (! SWI_vector_installed)
ARMul_OSHandleSWI (state, SWI_Breakpoint);
else
!
! /* BKPT - normally this will cause an abort, but for the
! XScale if bit 31 in register 10 of coprocessor 14 is
! clear, then this is treated as a no-op. */
! if (state->is_XScale)
! {
! if (read_cp14_reg (10) & (1UL << 31))
! {
! ARMword value;
!
! value = read_cp14_reg (10);
! value &= ~0x1c;
! value |= 0xc;
!
! write_cp14_reg (10, value);
! write_cp15_reg (5, 0, 0, 0x200); /* Set FSR. */
! write_cp15_reg (6, 0, 0, pc); /* Set FAR. */
! }
! else
! break;
! }
ARMul_Abort (state, ARMul_PrefetchAbortV);
break;
--- 1427,1439 ----
if (! SWI_vector_installed)
ARMul_OSHandleSWI (state, SWI_Breakpoint);
else
! {
! /* BKPT - normally this will cause an abort, but on the
! XScale we must check the DCSR. */
! XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc);
! if (!XScale_debug_moe (state, ARMul_CP14_R10_MOE_BT))
! break;
! }
ARMul_Abort (state, ARMul_PrefetchAbortV);
break;
*************** ARMul_Emulate26 (register ARMul_State *
*** 3427,3432 ****
--- 3484,3490 ----
case 0xff:
if (instr == ARMul_ABORTWORD && state->AbortAddr == pc)
{ /* a prefetch abort */
+ XScale_set_fsr_far (state, ARMul_CP15_R5_MMU_EXCPT, pc);
ARMul_Abort (state, ARMul_PrefetchAbortV);
break;
}
*************** LoadMult (ARMul_State * state, ARMword i
*** 4296,4302 ****
if (!state->abortSig && !state->Aborted)
state->Reg[temp++] = dest;
else if (!state->Aborted)
! state->Aborted = ARMul_DataAbortV;
for (; temp < 16; temp++) /* S cycles from here on */
if (BIT (temp))
--- 4354,4363 ----
if (!state->abortSig && !state->Aborted)
state->Reg[temp++] = dest;
else if (!state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
for (; temp < 16; temp++) /* S cycles from here on */
if (BIT (temp))
*************** LoadMult (ARMul_State * state, ARMword i
*** 4306,4312 ****
if (!state->abortSig && !state->Aborted)
state->Reg[temp] = dest;
else if (!state->Aborted)
! state->Aborted = ARMul_DataAbortV;
}
if (BIT (15) && !state->Aborted)
--- 4367,4376 ----
if (!state->abortSig && !state->Aborted)
state->Reg[temp] = dest;
else if (!state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
}
if (BIT (15) && !state->Aborted)
*************** LoadSMult (ARMul_State * state, ARMword
*** 4362,4368 ****
if (!state->abortSig)
state->Reg[temp++] = dest;
else if (!state->Aborted)
! state->Aborted = ARMul_DataAbortV;
for (; temp < 16; temp++) /* S cycles from here on */
if (BIT (temp))
--- 4426,4435 ----
if (!state->abortSig)
state->Reg[temp++] = dest;
else if (!state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
for (; temp < 16; temp++) /* S cycles from here on */
if (BIT (temp))
*************** LoadSMult (ARMul_State * state, ARMword
*** 4372,4378 ****
if (!state->abortSig && !state->Aborted)
state->Reg[temp] = dest;
else if (!state->Aborted)
! state->Aborted = ARMul_DataAbortV;
}
if (BIT (15) && !state->Aborted)
--- 4439,4448 ----
if (!state->abortSig && !state->Aborted)
state->Reg[temp] = dest;
else if (!state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
}
if (BIT (15) && !state->Aborted)
*************** StoreMult (ARMul_State * state, ARMword
*** 4464,4470 ****
ARMul_StoreWordN (state, address, state->Reg[temp++]);
#endif
if (state->abortSig && !state->Aborted)
! state->Aborted = ARMul_DataAbortV;
if (BIT (21) && LHSReg != 15)
LSBase = WBBase;
--- 4534,4543 ----
ARMul_StoreWordN (state, address, state->Reg[temp++]);
#endif
if (state->abortSig && !state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
if (BIT (21) && LHSReg != 15)
LSBase = WBBase;
*************** StoreMult (ARMul_State * state, ARMword
*** 4475,4481 ****
address += 4;
ARMul_StoreWordS (state, address, state->Reg[temp]);
if (state->abortSig && !state->Aborted)
! state->Aborted = ARMul_DataAbortV;
}
if (state->Aborted)
{
--- 4548,4557 ----
address += 4;
ARMul_StoreWordS (state, address, state->Reg[temp]);
if (state->abortSig && !state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
}
if (state->Aborted)
{
*************** StoreSMult (ARMul_State * state, ARMword
*** 4537,4543 ****
ARMul_StoreWordN (state, address, state->Reg[temp++]);
#endif
if (state->abortSig && !state->Aborted)
! state->Aborted = ARMul_DataAbortV;
if (BIT (21) && LHSReg != 15)
LSBase = WBBase;
--- 4613,4622 ----
ARMul_StoreWordN (state, address, state->Reg[temp++]);
#endif
if (state->abortSig && !state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
if (BIT (21) && LHSReg != 15)
LSBase = WBBase;
*************** StoreSMult (ARMul_State * state, ARMword
*** 4548,4554 ****
address += 4;
ARMul_StoreWordS (state, address, state->Reg[temp]);
if (state->abortSig && !state->Aborted)
! state->Aborted = ARMul_DataAbortV;
}
if (state->Mode != USER26MODE && state->Mode != USER32MODE)
--- 4627,4636 ----
address += 4;
ARMul_StoreWordS (state, address, state->Reg[temp]);
if (state->abortSig && !state->Aborted)
! {
! XScale_set_fsr_far(state, ARMul_CP15_R5_ST_ALIGN, address);
! state->Aborted = ARMul_DataAbortV;
! }
}
if (state->Mode != USER26MODE && state->Mode != USER32MODE)
Index: armemu.h
===================================================================
RCS file: /cvs/src/src/sim/arm/armemu.h,v
retrieving revision 1.10
diff -p -r1.10 armemu.h
*** armemu.h 2000/11/30 01:55:12 1.10
--- armemu.h 2001/01/10 05:18:31
*************** extern void ARMul_CoProAttach (ARMul
*** 490,495 ****
ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
extern void ARMul_CoProDetach (ARMul_State *, unsigned);
! extern void write_cp15_reg (unsigned, unsigned, unsigned, ARMword);
extern void write_cp14_reg (unsigned, ARMword);
extern ARMword read_cp14_reg (unsigned);
--- 490,495 ----
ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
extern void ARMul_CoProDetach (ARMul_State *, unsigned);
! extern void write_cp15_reg (ARMul_State *, unsigned, unsigned, unsigned, ARMword);
extern void write_cp14_reg (unsigned, ARMword);
extern ARMword read_cp14_reg (unsigned);
Index: arminit.c
===================================================================
RCS file: /cvs/src/src/sim/arm/arminit.c,v
retrieving revision 1.6
diff -p -r1.6 arminit.c
*** arminit.c 2000/11/30 01:55:12 1.6
--- arminit.c 2001/01/10 05:18:31
*************** ARMul_NewState (void)
*** 106,111 ****
--- 106,114 ----
state->OSptr = NULL;
state->CommandLine = NULL;
+ state->CP14R0_CCD = -1;
+ state->LastTime = 0;
+
state->EventSet = 0;
state->Now = 0;
state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
*************** ARMul_Abort (ARMul_State * state, ARMwor
*** 299,308 ****
SETABORT (IBIT, SVC26MODE, isize);
break;
case ARMul_IRQV: /* IRQ */
! SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
break;
case ARMul_FIQV: /* FIQ */
! SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
break;
}
if (ARMul_MODE32BIT)
--- 302,315 ----
SETABORT (IBIT, SVC26MODE, isize);
break;
case ARMul_IRQV: /* IRQ */
! if (!state->is_XScale
! || (state->CPRead[13](state, 0, 0) & ARMul_CP13_R0_IRQ))
! SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
break;
case ARMul_FIQV: /* FIQ */
! if (!state->is_XScale
! || (state->CPRead[13](state, 0, 0) & ARMul_CP13_R0_FIQ))
! SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
break;
}
if (ARMul_MODE32BIT)
Index: armvirt.c
===================================================================
RCS file: /cvs/src/src/sim/arm/armvirt.c,v
retrieving revision 1.3
diff -p -r1.3 armvirt.c
*** armvirt.c 2000/07/04 08:00:19 1.3
--- armvirt.c 2001/01/10 05:18:32
*************** freed as they might be needed again. A s
*** 24,29 ****
--- 24,30 ----
defined to generate aborts. */
#include "armopts.h"
+ #include "armos.h"
#include "armdefs.h"
#include "ansidecl.h"
*************** GetWord (ARMul_State * state, ARMword ad
*** 61,66 ****
--- 62,69 ----
ARMword **pagetable;
ARMword *pageptr;
+ XScale_check_memacc (state, &address, 0);
+
page = address >> PAGEBITS;
offset = (address & OFFSETBITS) >> 2;
pagetable = (ARMword **) state->MemDataPtr;
*************** PutWord (ARMul_State * state, ARMword ad
*** 93,98 ****
--- 96,103 ----
ARMword offset;
ARMword **pagetable;
ARMword *pageptr;
+
+ XScale_check_memacc (state, &address, 1);
page = address >> PAGEBITS;
offset = (address & OFFSETBITS) >> 2;