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AM33 assembler: avoid using non-promoting AM30 insns


After the assembler patch I posted yesterday, that recognizes AM30
instructions in AM33 mode, a simple problem showed up.  Some AM30
instructions didn't allow for promotion of the immediate operands,
whereas AM33 offers similar insns with wider immediate operands, so
they must be allowed to promote.  Here's a patch that fixes this
problem.  Ok to install?  Release branches?

Index: opcodes/ChangeLog
by  Alexandre Oliva  <aoliva@cygnus.com>

	* m10300-opc.c (mov, AM30): Move AM30 non-promoting mov insns
	after AM33's, so that arguments can promote on AM33.

Index: opcodes/m10300-opc.c
===================================================================
RCS file: /cvs/cvsfiles/devo/opcodes/m10300-opc.c,v
retrieving revision 1.32
diff -u -r1.32 m10300-opc.c
--- opcodes/m10300-opc.c	2000/04/01 22:03:38	1.32
+++ opcodes/m10300-opc.c	2000/04/14 18:06:15
@@ -549,11 +549,7 @@
 { "mov",	0xfc910000,  0xfff30000,  0,    FMT_D4, 0,	{DM1, MEM2(IMM32, SP)}},
 { "mov",	0xfc300000,  0xfff00000,  0,    FMT_D4, 0,	{AM1, MEM2(IMM32,AN0)}},
 { "mov",	0xfc900000,  0xfff30000,  0,    FMT_D4, 0,	{AM1, MEM2(IMM32, SP)}},
-/* These non-promoting variants need to come after all the other memory
-   moves.  */
-{ "mov",	0xf8f000,    0xfffc00,    0,    FMT_D1, AM30,	{MEM2(SD8N, AM0), SP}},
-{ "mov",	0xf8f400,    0xfffc00,    0,    FMT_D1, AM30,	{SP, MEM2(SD8N, AN0)}},
-/* These are the same as the previous non-promoting versions.  The am33
+/* These are the same as the AM30 non-promoting versions below.  The am33
    does not have restrictions on the offsets used to load/store the stack
    pointer.  */
 { "mov",	0xf8f000,    0xfffc00,    0,    FMT_D1, AM33,	{MEM2(SD8, AM0), SP}},
@@ -572,6 +568,11 @@
 { "mov",	0xfe1a0000,  0xffff0000,  0,    FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8, RN0)}},
 { "mov",	0xfe8a0000,  0xffff0f00,  0,    FMT_D9, AM33,	{MEM2(IMM32_HIGH8, SP), RN2}},
 { "mov",	0xfe9a0000,  0xffff0f00,  0,    FMT_D9, AM33,	{RM2, MEM2(IMM32_HIGH8, SP)}},
+/* These non-promoting variants need to come after all the other
+   memory moves, so that they don't prevent newer CPU's operands from
+   promoting. */
+{ "mov",	0xf8f000,    0xfffc00,    0,    FMT_D1, AM30,	{MEM2(SD8N, AM0), SP}},
+{ "mov",	0xf8f400,    0xfffc00,    0,    FMT_D1, AM30,	{SP, MEM2(SD8N, AN0)}},
 
 { "movu",	0xfb180000,  0xffff0000,  0,    FMT_D7, AM33,	{IMM8, RN02}},
 { "movu",	0xfd180000,  0xffff0000,  0,    FMT_D8, AM33,	{IMM24, RN02}},

-- 
Alexandre Oliva    Enjoy Guaranį, see http://www.ic.unicamp.br/~oliva/
Cygnus Solutions, a Red Hat company        aoliva@{redhat, cygnus}.com
Free Software Developer and Evangelist    CS PhD student at IC-Unicamp
oliva@{lsd.ic.unicamp.br, gnu.org}   Write to mailing lists, not to me

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