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src/sim/testsuite/sim/cr16 addb.cgs addd.cgs a ...


CVSROOT:	/cvs/src
Module name:	src
Changes by:	swami@sourceware.org	2008-05-05 09:52:46

Modified files:
	sim/testsuite/sim/cr16: addb.cgs addd.cgs addi.cgs andb.cgs 
	                        andd.cgs andw.cgs ashub.cgs ashub_i.cgs 
	                        ashud.cgs ashud_i.cgs ashuw.cgs 
	                        ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs 
	                        jump.cgs loadd.cgs loadw.cgs lshb.cgs 
	                        lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs 
	                        lshw_i.cgs movb.cgs movd.cgs movw.cgs 
	                        movxb.cgs movxw.cgs movzb.cgs movzw.cgs 
	                        mulb.cgs muluw.cgs mulw.cgs orb.cgs 
	                        ord.cgs orw.cgs pop1.cgs pop2.cgs 
	                        pop3.cgs popret1.cgs popret2.cgs 
	                        popret3.cgs push1.cgs push2.cgs 
	                        push3.cgs 
Added files:
	sim/testsuite/sim/cr16: cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs 
	                        tbitb.cgs tbit.cgs tbitw.cgs 

Log message:
	Update testcase comment.
	addb.cgs addd.cgs addi.cgs andb.cgs andd.cgs andw.cgs
	ashub.cgs ashub_i.cgs ashud.cgs ashud_i.cgs ashuw.cgs
	ashuw_i.cgs cmpi.cgs cmpw.cgs jlt.cgs jump.cgs loadd.cgs
	loadw.cgs lshb.cgs lshb_i.cgs lshd.cgs lshd_i.cgs lshw.cgs
	lshw_i.cgs movb.cgs movd.cgs movw.cgs movxb.cgs movxw.cgs
	movzb.cgs movzw.cgs mulb.cgs muluw.cgs mulw.cgs orb.cgs
	ord.cgs orw.cgs pop1.cgs pop2.cgs pop3.cgs popret1.cgs
	popret2.cgs popret3.cgs push1.cgs push2.cgs push3.cgs
	
	Added BIT operation testcases:
	cbitb.cgs cbitw.cgs sbitb.cgs sbitw.cgs tbitb.cgs tbit.cgs and tbitw.cgs

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/cbitb.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/cbitw.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/sbitb.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/sbitw.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/tbitb.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/tbit.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/tbitw.cgs.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/addb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/addd.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/addi.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/andb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/andd.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/andw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ashub.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ashub_i.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ashud.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ashud_i.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ashuw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ashuw_i.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/cmpi.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/cmpw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/jlt.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/jump.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/loadd.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/loadw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/lshb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/lshb_i.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/lshd.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/lshd_i.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/lshw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/lshw_i.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movd.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movxb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movxw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movzb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/movzw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/mulb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/muluw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/mulw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/orb.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/ord.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/orw.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/pop1.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/pop2.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/pop3.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/popret1.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/popret2.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/popret3.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/push1.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/push2.cgs.diff?cvsroot=src&r1=1.1&r2=1.2
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/cr16/push3.cgs.diff?cvsroot=src&r1=1.1&r2=1.2


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