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src/sim ChangeLog cris/arch.c cris/arch.h cris ...


CVSROOT:	/cvs/src
Module name:	src
Changes by:	hp@sourceware.org	2007-10-22 16:06:38

Modified files:
	sim            : ChangeLog 
	sim/cris       : arch.c arch.h cpuall.h cpuv10.c cpuv10.h 
	                 cpuv32.c cpuv32.h cris-desc.c cris-desc.h 
	                 cris-opc.h decodev10.c decodev10.h decodev32.c 
	                 decodev32.h modelv10.c modelv32.c 
	                 semcrisv10f-switch.c semcrisv32f-switch.c 

Log message:
	* cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c,
	cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c,
	cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c,
	cris/decodev10.h, cris/decodev32.c, cris/decodev32.h,
	cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c,
	cris/semcrisv32f-switch.c: Regenerate.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/ChangeLog.diff?cvsroot=src&r1=1.94&r2=1.95
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/arch.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/arch.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cpuall.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv10.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv10.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv32.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cpuv32.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cris-desc.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cris-desc.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/cris-opc.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/decodev10.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/decodev10.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/decodev32.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/decodev32.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/modelv10.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/modelv32.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/semcrisv10f-switch.c.diff?cvsroot=src&r1=1.5&r2=1.6
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/cris/semcrisv32f-switch.c.diff?cvsroot=src&r1=1.5&r2=1.6


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