src/sim mips/ChangeLog mips/configure mips/con ...

[ths at sourceware dot org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	ths@sourceware.org	2007-02-20 13:28:56

Modified files:
	sim/mips       : ChangeLog configure configure.ac Makefile.in 
	                 dsp.igen mips.igen 
	sim/testsuite/sim/mips: ChangeLog basic.exp utils-dsp.inc 
Added files:
	sim/mips       : dsp2.igen 
	sim/testsuite/sim/mips: mips32-dsp2.s 

Log message:
	[ gas/ChangeLog ]
	* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
	ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
	(macro_build): Add case '2'.
	(macro): Expand M_BALIGN to nop, packrl.ph or balign.
	(validate_mips_insn): Add support for balign instruction.
	(mips_ip): Handle DSP R2 instructions. Support balign instruction.
	(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
	md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
	command line options.
	(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
	(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
	* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
	.set dspr2, .set nodspr2.
	
	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
	DSP R2.
	* gas/mips/mips.exp: Run new test.
	
	[ include/opcode/Changelog ]
	* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
	(INSN_DSPR2): Add flag for DSP R2 instructions.
	(M_BALIGN): New macro.
	
	[ opcodes/ChangeLog ]
	* mips-dis.c (mips_arch_choices): Add DSP R2 support.
	(print_insn_args): Add support for balign instruction.
	* mips-opc.c (D33): New shortcut for DSP R2 instructions.
	(mips_builtin_opcodes): Add DSP R2 instructions.
	
	[ sim/mips/ChangeLog ]
	* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
	* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
	Add dsp2 to sim_igen_machine.
	* configure: Regenerate.
	* dsp.igen (do_ph_op): Add MUL support when op = 2.
	(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
	(mulq_rs.ph): Use do_ph_mulq.
	(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
	* mips.igen: Add dsp2 model and include dsp2.igen.
	(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
	for *mips32r2, *mips64r2, *dsp.
	(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
	for *mips32r2, *mips64r2, *dsp2.
	* dsp2.igen: New file for MIPS DSP REV 2 ASE.
	
	[ sim/testsuite/sim/mips/ChangeLog ]
	* basic.exp: Run the dsp2 test.
	* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
	* mips32-dsp2.s: New test.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/dsp2.igen.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/ChangeLog.diff?cvsroot=src&r1=1.137&r2=1.138
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/configure.diff?cvsroot=src&r1=1.29&r2=1.30
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/configure.ac.diff?cvsroot=src&r1=1.10&r2=1.11
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/Makefile.in.diff?cvsroot=src&r1=1.12&r2=1.13
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/dsp.igen.diff?cvsroot=src&r1=1.3&r2=1.4
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/mips/mips.igen.diff?cvsroot=src&r1=1.63&r2=1.64
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/mips/mips32-dsp2.s.diff?cvsroot=src&r1=NONE&r2=1.1
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/mips/ChangeLog.diff?cvsroot=src&r1=1.14&r2=1.15
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/mips/basic.exp.diff?cvsroot=src&r1=1.8&r2=1.9
http://sourceware.org/cgi-bin/cvsweb.cgi/src/sim/testsuite/sim/mips/utils-dsp.inc.diff?cvsroot=src&r1=1.2&r2=1.3