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From: Scott Howard <scott@objsw.com> >From the compiler's point of view, the 68360 and the 68332 are >identical, because they both implement the same instruction set; so >you're not losing any functionality by not having a '-m68360' command >line option. The more I think about this, I'm not completely convinced. In the MC68360 User's Manual, section 5.1, second paragraph, it initially says: The CPU32+ core is a CPU32 core with its bus interface unit modified to connect directly to the 32-bit IMB... I assume this wouldn't affect the compiler, so that supports your statement. But in the third paragraph: The CPU32+ also supports byte-misaligned operands. [...] CPU32-based MC68300 allow long-word operand transfers at odd-word addresses, but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. This probably isn't a major feature, but it implies that the '360 isn't a stock CPU32 core after all. Then it begins to make statements like: The CPU32+ has four bits (SZ1, SZ0 and SZC1, SCZ0) in the software status word (SSW) that are new or have changed definitions. But it doesn't say "new" with respect to what: the CPU32? This might make more of a difference. I've never tried to dig through the machine description, but I'm beginning to wonder now just how close the CPU32 and CPU32+ really are. -- John A. Breen jab3@hotmail.com ______________________________________________________ Get Your Private, Free Email at http://www.hotmail.com _______________________________________________ New CrossGCC FAQ: http://www.objsw.com/CrossGCC _______________________________________________ To remove yourself from the crossgcc list, send mail to crossgcc-request@cygnus.com with the text 'unsubscribe' (without the quotes) in the body of the message.