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Re: CGEN_DIS_HASH: how to get endianness and/or instruction size?
Hi -
On Thu, Jan 25, 2007 at 08:30:11PM +0000, Joern Rennecke wrote:
> I've seen that, but it assumes that if the top 16 its are zero,
> the instruction can be hashed as a 16 bit instruction. That is not
> the case for ARCompact. [...]
Where are the bits that allow the insn to be decoded as a branch? How
the hardware know whether it's a 16- or 32-bit insn? Those are the
kind of bits are what are normally mingled into the hash. Maybe your
base_insn designation is too small.
> > It is important to realize though that this disassembler hashing
> > widget is strictly an optimization. [...]
>
> I can only verify this positively when I've completely finished the
> port so that other people can use it...
Indeed, but if you can accept a lesser standard of proof, you could
leave this part of the port till the end.
- FChE