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Re: Insns with similar mnemonics


I usually end up ordering the insns in the .cpu file so that the most restrictive insn (in your case move13meml) appears first. CGEN currently attempts the insns in the order in which they appear in the .cpu file. Even with a parse handler, this is often necessary to prevent an unintended variant from parsing successfully.

I've never seen this ordering behavior documented anywhere. It sould be nice if we could get a definitive statement in the documentation about it, since many existing ports rely on it.

Dave

Jan Zizka wrote:

Hi!

I have a small problem with correcly assembling following insns (only examle):

move x:(r0+symbol1),x0
move x:symbol2,x0

since the pharenteses might be aswell part of a symbol the first instruction is
interpreted as it would be second one. This will of course make r0, which is
really a register, undefined symbol. Now I have added my own parse function for
that, but it's really not elegat :(. Any suggestions? See my insn definitions
below:

(dni move13meml/allreg "move x:(Rn+xxxx),DDDDD"
	  ()
	  ("move x:($r+$imm16),$d5cap")
	  (+ (f-op-4 #xF) d5cap (f-op-bit-2/6 #x10) r imm16)
	  ()
	  ()
)

(dni move14mem/allreg "move x:imm16,DDDDD"
	  ()
	  ("move x:$imm16,$d5cap")
	  (+ (f-op-4 #xF) d5cap (f-op--7 #x54) imm16)
	  ()
	  ()
)

Thanks!
Jan





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