This is the mail archive of the
cgen@sources.redhat.com
mailing list for the CGEN project.
Confusion: setup-semantics? PC not updated? Immediate operands?
- From: Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>
- To: cgen at sources dot redhat dot com
- Date: Tue, 29 Jan 2002 01:03:26 +0100
- Subject: Confusion: setup-semantics? PC not updated? Immediate operands?
Hm, I can't get anything out from setup-semantics in a
define-isa, like (example only):
(define-isa
(name cris)
(base-insn-bitsize 16)
(default-insn-word-bitsize 16)
(liw-insns 1)
(parallel-insns 1)
(setup-semantics
(error "Nothing happens"))
)
This when generating that big GCC-specific C switch
<arch>-switch.c, which seems generated from sim-cpu.scm. From
what little scheme I understand (I'm blissfully naive), it seems
only sid-cpu.scm, not sim-cpu.scm, supports setup-semantics.
I'd use it for purposes similar to that of arm.cpu.
Should it work?
On a related matter, it seems pc isn't updated for non-CTI
insns; it's value is that of the first insn in the chain.
I need it as an operand in non-CTI insns.
Oh right, there's a further related issue in the pipeline: how
do I best specify 16-bit and 32-bit immediate operands? The
immediate value is coded as indirect-pc-postincrement, "[pc+]",
where pc is mapped as one of the 16 general registers. I'm
currently hacking the update of pc in sim/cris/mloop.in in the
case for "xextract-pbb" (based on fr30/mloop.in). I guess it's
best to have a specific case for the "[pc+]" operand (leaving
cases for other registers in a generally specified insn), but I
need to at least tell CGEN to skip two or four bytes. I just
can't see where to specify that.
brgds, H-P