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re: generalizing the delay rtx function
- To: "Frank Ch. Eigler" <fche at redhat dot com>
- subject: re: generalizing the delay rtx function
- From: matthew green <mrg at cygnus dot com>
- Date: Thu, 15 Mar 2001 11:42:55 +1100
- Cc: cgen at sources dot redhat dot com
- organisation: Red Hat, Inc.
On Wed, Mar 14, 2001 at 06:40:05PM +1100, matthew green wrote:
: [...]
: is this possible? eg, (sparc) if i do:
:=20
: ba foo
: ld [%l1 + 4], %o0
: vs.
: ba foo
: tst %o0
:=20
: the load can take *much* longer than the tst?
I'm not sure I guess correctly at your point; is it that
these two code sequences require a different number of
clock cycles to run on a SPARC chip? If so, yes, but
the delay is not a programmer-visible one, so the=20
proposed extensions to the delay rtx would not be used
to model it.
you said the delay rtx would be changed to indicate the number
of "instruction cycles" before the effect is seen. my example
above shows a case where this isn't going to be known. if you
didn't mean "instruction cycles" but really "instructions" then
my point is meaningless.
.mrg.