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Re: How to handle MIPS-like general register 0?
- To: greg at mcgary dot org (Greg McGary)
- Subject: Re: How to handle MIPS-like general register 0?
- From: fche at redhat dot com (Frank Ch. Eigler)
- Date: 18 Jan 2001 07:41:16 -0500
- Cc: cgen at sourceware dot cygnus dot com
- References: <200101180826.BAA02239.cygnus.local.cgen@kayak.mcgary.org>
greg@mcgary.org (Greg McGary) writes:
: What's the recommended way of handling simulator semantics for a
: general register zero that always reads as 0, and writes as bit-bucket
: (as for MIPS)? [...]
Another way is to add an explicit register-setting statement into each
iteration of the instruction evaluation loop. One trades the cost of
a conditional branch (by intercepting the register-setting hooks) for
the cost of fixed overhead (always clearing the sucker).
- FChE