[PATCH] RISC-V: Fix .p2align is not at smallest instruction

[Kuan-Lin Chen <kuanlinchentw at gmail dot com>]

Hi,

As far as I know, RISC-V compilers (LLVM & GCC) doesn't mix code and data
in the same section.  But we cannot avoid users mixing them in manual assembly
code.

Example:
.text
.globl main
.option norvc
.option relax
main:
        nop
        .byte 0x99
        .byte 0x99
        .byte 0x99
.p2align 1
        nop

After assembling:
00000000 <main>:
   0:   00000013                nop
   4:   9999                    andi    a1,a1,-26
   6:   1399                    addi    t2,t2,-26
   8:   0000                    unimp

The second nop doesn't align to 2-byte alignment.

BTW, the test case ld/testsuite/ld-riscv-elf/align-1.d is for
commit(ed0816bd936492aa7dc00e4fbbf8ff8de1253854).

bfd/ChangeLog:
* elfnn-riscv.c (_bfd_riscv_relax_align): Fill nops for alignment.
* elfxx-riscv.c (howto_table): Modify size of R_RISCV_ALIGN.

gas/ChangeLog:
* config/tc-riscv.c (md_apply_fix): Adjust BFD_RELOC_RISCV_ALIGN addend.
* (riscv_frag_align_code): New the alignment fragments.
* (riscv_handle_align): Fill rs_align_code fragments.
* testsuite/gas/riscv/align-2.d: New test.
* testsuite/gas/riscv/align-2.s: New test.
* testsuite/gas/riscv/align-3.d: New test.
* testsuite/gas/riscv/align-3.s: New test.
* testsuite/gas/riscv/align-4.d: New test.
* testsuite/gas/riscv/align-4.s: New test.
* testsuite/gas/riscv/align-5.d: New test.
* testsuite/gas/riscv/align-5.s: New test.

ld/ChangeLog:
* testsuite/ld-riscv-elf/align-1.d: New test.
* testsuite/ld-riscv-elf/align-1.s  New test.
* testsuite/ld-riscv-elf/align-2.d  New test.
* testsuite/ld-riscv-elf/align-2.s  New test.
* testsuite/ld-riscv-elf/align-3.d  New test.
* testsuite/ld-riscv-elf/align-3.s  New test.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add align-1, align-2 and
align-3.


-- 
Best regards,
Kuan-Lin Chen.
kuanlinchentw@gmail.com

Attachment: 0001-RISC-V-Fix-.p2align-is-not-at-smallest-instruction-a.patch
Description: Binary data