From fe962e8a9593643096093865f5245857753db97e Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen@sifive.com>
Date: Tue, 30 Jul 2019 00:28:52 -0700
Subject: [PATCH 2/2] RISC-V: Rearrange frsr, frcsr, fssr and fscsr
 instructions since frsr and fssr are obsolete.

        opcodes/
        * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr,
        fssr, fscsr.

        gas/
        * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
        * testsuite/gas/riscv/priv-reg.d: Update.
---
 gas/ChangeLog                       |  3 +++
 gas/testsuite/gas/riscv/alias-csr.d | 23 +++++++++++++++++++++++
 gas/testsuite/gas/riscv/priv-reg.d  |  2 +-
 opcodes/ChangeLog                   |  3 +++
 opcodes/riscv-opc.c                 |  6 +++---
 5 files changed, 33 insertions(+), 4 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/alias-csr.d

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bf2e5a6..4d6f902 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -5,6 +5,9 @@
 	* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
 	-Mno-aliases.
 
+	* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
+	* testsuite/gas/riscv/priv-reg.d: Update.
+
 2019-07-24  Nick Clifton  <nickc@redhat.com>
 
 	* po/sv.po: Updated Swedish translation.
diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
new file mode 100644
index 0000000..af5c591
--- /dev/null
+++ b/gas/testsuite/gas/riscv/alias-csr.d
@@ -0,0 +1,23 @@
+#source: alias-csr.s
+#as: -march=rv64if
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <alias_csr>:
+[ 	]+0:[ 	]+003022f3[ 	]+frcsr[ 	]+t0
+[ 	]+4:[ 	]+003392f3[ 	]+fscsr[ 	]+t0,t2
+[ 	]+8:[ 	]+00339073[ 	]+fscsr[ 	]+t2
+[ 	]+c:[ 	]+002022f3[ 	]+frrm[ 	]+t0
+[ 	]+10:[ 	]+002312f3[ 	]+fsrm[ 	]+t0,t1
+[ 	]+14:[ 	]+00231073[ 	]+fsrm[ 	]+t1
+[ 	]+18:[ 	]+002fd2f3[ 	]+fsrmi[ 	]+t0,31
+[ 	]+1c:[ 	]+002fd073[ 	]+fsrmi[ 	]+zero,31
+[ 	]+20:[ 	]+001022f3[ 	]+frflags[ 	]+t0
+[ 	]+24:[ 	]+001312f3[ 	]+fsflags[ 	]+t0,t1
+[ 	]+28:[ 	]+00131073[ 	]+fsflags[ 	]+t1
+[ 	]+2c:[ 	]+001fd2f3[ 	]+fsflagsi[ 	]+t0,31
+[ 	]+30:[ 	]+001fd073[ 	]+fsflagsi[ 	]+zero,31
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
index 9ec5d97..d8ec868 100644
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ b/gas/testsuite/gas/riscv/priv-reg.d
@@ -17,7 +17,7 @@ Disassembly of section .text:
 [ 	]+1c:[ 	]+04402573[ 	]+csrr[ 	]+a0,uip
 [ 	]+20:[ 	]+00102573[ 	]+frflags[ 	]+a0
 [ 	]+24:[ 	]+00202573[ 	]+frrm[ 	]+a0
-[ 	]+28:[ 	]+00302573[ 	]+frsr[ 	]+a0
+[ 	]+28:[ 	]+00302573[ 	]+frcsr[ 	]+a0
 [ 	]+2c:[ 	]+c0002573[ 	]+rdcycle[ 	]+a0
 [ 	]+30:[ 	]+c0102573[ 	]+rdtime[ 	]+a0
 [ 	]+34:[ 	]+c0202573[ 	]+rdinstret[ 	]+a0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e86d387..02f3c07 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -6,6 +6,9 @@
 	Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags,
 	fsflagsi to alias instructions.
 
+	* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
+	fscsr.
+
 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6fc5ac6..b7e8d79 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -496,12 +496,12 @@ const struct riscv_opcode riscv_opcodes[] =
 {"remuw",    64, {"M", 0}, "d,s,t",  MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
 /* Single-precision floating-point instruction subset */
-{"frsr",      0, {"F", 0},   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
-{"fssr",      0, {"F", 0},   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
-{"fssr",      0, {"F", 0},   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
 {"frcsr",     0, {"F", 0},   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"frsr",      0, {"F", 0},   "d",  MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
 {"fscsr",     0, {"F", 0},   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
 {"fscsr",     0, {"F", 0},   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"fssr",      0, {"F", 0},   "s",  MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fssr",      0, {"F", 0},   "d,s",  MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
 {"frrm",      0, {"F", 0},   "d",  MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
 {"fsrm",      0, {"F", 0},   "s",  MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS },
 {"fsrm",      0, {"F", 0},   "d,s",  MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
-- 
2.7.4

