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Re: [PATCH v2 5/5] RISC-V: Add r4 format for r type with 4 register operands

From: Jim Wilson <jimw at sifive dot com>
To: Kito Cheng <kito dot cheng at sifive dot com>
Cc: Binutils <binutils at sourceware dot org>
Date: Fri, 5 Jul 2019 12:32:10 +0800
Subject: Re: [PATCH v2 5/5] RISC-V: Add r4 format for r type with 4 register operands
References: <20190702095801.32062-1-kito.cheng@sifive.com> <20190702095801.32062-5-kito.cheng@sifive.com>

On Tue, Jul 2, 2019 at 5:58 PM Kito Cheng <kito.cheng@sifive.com> wrote:
> gas/ChangeLog:
>         * doc/c-riscv.texi (Instruction Formats): Add r4 type.
>         * testsuite/gas/riscv/insn.d: Add testcase for r4 type.
>         * testsuite/gas/riscv/insn.s: Ditto.
> opcodes/ChangeLog:
>         * riscv-opc.c (riscv_insn_types): Add r4 type.

This is OK.

Jim

References:
- [PATCH v2 1/5] RISC-V: Fix doc for .insn
  - From: Kito Cheng
- [PATCH v2 5/5] RISC-V: Add r4 format for r type with 4 register operands
  - From: Kito Cheng

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