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Re: [PATCH, committed] X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Thu, 3 Nov 2016 09:57:51 -0700
- Subject: Re: [PATCH, committed] X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
- Authentication-results: sourceware.org; auth=none
- References: <20161103161838.GA23454@intel.com> <581B7487020000780011C0CF@prv-mh.provo.novell.com> <CAMe9rOrJ0T_28r=Qdu0Qk6-wY8Yu_e8N_9=5T2=NsaTs1JR9=A@mail.gmail.com>
On Thu, Nov 3, 2016 at 9:45 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Nov 3, 2016 at 9:31 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 03.11.16 at 17:18, <hongjiu.lu@intel.com> wrote:
>>> Update x86 disassembler to treat opcode 0x82 as an aliase of opcode 0x80
>>> in 32-bit mode.
>>>
>>> gas/
>>>
>>> PR binutils/20754
>>> * testsuite/gas/i386/opcode.s: Add tests for opcode 0x82.
>>> * testsuite/gas/i386/opcode-intel.d: Updated.
>>> * testsuite/gas/i386/opcode.d: Likewise.
>>>
>>> opcodes/
>>>
>>> PR binutils/20754
>>> * i386-dis.c (REG_82): New.
>>> (X86_64_82_REG_0): Likewise.
>>> (X86_64_82_REG_1): Likewise.
>>> (X86_64_82_REG_2): Likewise.
>>> (X86_64_82_REG_3): Likewise.
>>> (X86_64_82_REG_4): Likewise.
>>> (X86_64_82_REG_5): Likewise.
>>> (X86_64_82_REG_6): Likewise.
>>> (X86_64_82_REG_7): Likewise.
>>
>> Why do you need all these? I've had a patch pending doing about the
>> same, but with fewer new identifiers.
>
> Nothing particular.
>
I checked in this patch to reuse opcode 0x80 decoder for opcode 0x82.
--
H.J.
From d039fef395c1b5fd781acaf1c611f96f654f5f91 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Thu, 3 Nov 2016 09:55:01 -0700
Subject: [PATCH] X86: Reuse opcode 0x80 decoder for opcode 0x82
Since opcode 0x82 is an alias of opcode 0x80, we can reuse opcode 0x80
decoder.
* i386-dis.c (REG_82): Removed.
(X86_64_82_REG_0): Likewise.
(X86_64_82_REG_1): Likewise.
(X86_64_82_REG_2): Likewise.
(X86_64_82_REG_3): Likewise.
(X86_64_82_REG_4): Likewise.
(X86_64_82_REG_5): Likewise.
(X86_64_82_REG_6): Likewise.
(X86_64_82_REG_7): Likewise.
(X86_64_82): New.
(dis386): Use X86_64_82 instead of REG_82.
(reg_table): Remove REG_82.
(x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
X86_64_82_REG_7.
---
opcodes/ChangeLog | 19 ++++++++++++++++
opcodes/i386-dis.c | 63 +++++-------------------------------------------------
2 files changed, 24 insertions(+), 58 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d0f8846..4c7ba8d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,24 @@
2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+ * i386-dis.c (REG_82): Removed.
+ (X86_64_82_REG_0): Likewise.
+ (X86_64_82_REG_1): Likewise.
+ (X86_64_82_REG_2): Likewise.
+ (X86_64_82_REG_3): Likewise.
+ (X86_64_82_REG_4): Likewise.
+ (X86_64_82_REG_5): Likewise.
+ (X86_64_82_REG_6): Likewise.
+ (X86_64_82_REG_7): Likewise.
+ (X86_64_82): New.
+ (dis386): Use X86_64_82 instead of REG_82.
+ (reg_table): Remove REG_82.
+ (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
+ X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
+ X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
+ X86_64_82_REG_7.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
PR binutils/20754
* i386-dis.c (REG_82): New.
(X86_64_82_REG_0): Likewise.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index b0bb5e8..22f77aa 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -706,7 +706,6 @@ enum
{
REG_80 = 0,
REG_81,
- REG_82,
REG_83,
REG_8F,
REG_C0,
@@ -1695,14 +1694,7 @@ enum
X86_64_63,
X86_64_6D,
X86_64_6F,
- X86_64_82_REG_0,
- X86_64_82_REG_1,
- X86_64_82_REG_2,
- X86_64_82_REG_3,
- X86_64_82_REG_4,
- X86_64_82_REG_5,
- X86_64_82_REG_6,
- X86_64_82_REG_7,
+ X86_64_82,
X86_64_9A,
X86_64_C4,
X86_64_C5,
@@ -2671,7 +2663,7 @@ static const struct dis386 dis386[] = {
/* 80 */
{ REG_TABLE (REG_80) },
{ REG_TABLE (REG_81) },
- { REG_TABLE (REG_82) },
+ { X86_64_TABLE (X86_64_82) },
{ REG_TABLE (REG_83) },
{ "testB", { Eb, Gb }, 0 },
{ "testS", { Ev, Gv }, 0 },
@@ -3409,17 +3401,6 @@ static const struct dis386 reg_table[][8] = {
{ "xorQ", { Evh1, Iv }, 0 },
{ "cmpQ", { Ev, Iv }, 0 },
},
- /* REG_82 */
- {
- { X86_64_TABLE (X86_64_82_REG_0) },
- { X86_64_TABLE (X86_64_82_REG_1) },
- { X86_64_TABLE (X86_64_82_REG_2) },
- { X86_64_TABLE (X86_64_82_REG_3) },
- { X86_64_TABLE (X86_64_82_REG_4) },
- { X86_64_TABLE (X86_64_82_REG_5) },
- { X86_64_TABLE (X86_64_82_REG_6) },
- { X86_64_TABLE (X86_64_82_REG_7) },
- },
/* REG_83 */
{
{ "addQ", { Evh1, sIb }, 0 },
@@ -6907,44 +6888,10 @@ static const struct dis386 x86_64_table[][2] = {
{ "outs{G|}", { indirDXr, Xz }, 0 },
},
- /* X86_64_82_REG_0 */
- {
- { "addA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_1 */
- {
- { "orA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_2 */
- {
- { "adcA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_3 */
+ /* X86_64_82 */
{
- { "sbbA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_4 */
- {
- { "andA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_5 */
- {
- { "subA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_6 */
- {
- { "xorA", { Ebh1, Ib }, 0 },
- },
-
- /* X86_64_82_REG_7 */
- {
- { "cmpA", { Eb, Ib }, 0 },
+ /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
+ { REG_TABLE (REG_80) },
},
/* X86_64_9A */
--
2.7.4