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[PATCH] Add support for yet some more new ISA 3.0 instructions.


This patch adds support for yet some more new instructions that were just
added (today!) to POWER ISA 3.0.  I've been told there will be no more
additions after these.

Tristan, I'd like to commit this to trunk in time to make 2.27, so that
2.27 supports all ISA 3.0 (ie, POWER9) instructions and since the format
for the setb instruction has changed.  Ok?

Peter


opcodes/
	* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
	(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
	mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
	xor3>: New mnemonics.
	<setb>: Change to a VX form instruction.
	(insert_sh6): Add support for rldixor.
	(extract_sh6): Likewise.

gas/
	* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
	mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
	setbool, xor3>: New tests.
	* testsuite/gas/ppc/power9.s: Likewise.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f3349e5..8106ab7 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -238,7 +238,11 @@ const struct powerpc_operand powerpc_operands[] =
 #define BOE BO + 1
   { 0x1e, 21, insert_boe, extract_boe, 0 },
 
-#define BH BOE + 1
+  /* The RM field in an X form instruction.  */
+#define RM BOE + 1
+  { 0x3, 11, NULL, NULL, 0 },
+
+#define BH RM + 1
   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The BT field in an X or XL form instruction.  */
@@ -786,8 +790,9 @@ const struct powerpc_operand powerpc_operands[] =
 #define EVUIMM_8 EVUIMM_4 + 1
   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 
-  /* The WS field.  */
+  /* The WS or DRM field in an X form instruction.  */
 #define WS EVUIMM_8 + 1
+#define DRM WS
   { 0x7, 11, NULL, NULL, 0 },
 
   /* PowerPC paired singles extensions.  */
@@ -2017,7 +2022,11 @@ insert_sh6 (unsigned long insn,
 	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 	    const char **errmsg ATTRIBUTE_UNUSED)
 {
-  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
+  /* SH6 operand in the rldixor instruction.  */
+  if (PPC_OP (insn) == 4)
+    return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
+  else
+    return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 }
 
 static long
@@ -2025,7 +2034,11 @@ extract_sh6 (unsigned long insn,
 	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 	     int *invalid ATTRIBUTE_UNUSED)
 {
-  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
+  /* SH6 operand in the rldixor instruction.  */
+  if (PPC_OP (insn) == 4)
+    return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
+  else
+    return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 }
 
 /* The SPR field in an XFX form instruction.  This is flipped--the
@@ -2608,6 +2621,9 @@ extract_vleil (unsigned long insn,
 /* A VX form instruction with a VA tertiary opcode.  */
 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
 
+#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
+#define VXASH_MASK VXASH (0x3f, 0x1f)
+
 /* An X form instruction.  */
 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 
@@ -2644,6 +2660,9 @@ extract_vleil (unsigned long insn,
 /* A X form instruction for Quad-Precision FP Instructions with RC bit.  */
 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
 
+/* An X form instruction with the RA bits specified as two ops.  */
+#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
+
 /* A Z form instruction with the RC bit specified.  */
 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
 
@@ -2696,6 +2715,9 @@ extract_vleil (unsigned long insn,
 /* An X form wait instruction with everything filled in except the WC field.  */
 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
 
+/* The mask for an XMMF form instruction.  */
+#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
+
 /* The mask for a Z form instruction.  */
 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
 #define Z2_MASK ZRC (0x3f, 0xff, 1)
@@ -3139,6 +3161,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"machhwu.",	XO (4,	12,0,1), XO_MASK,    MULHW,	0,		{RT, RA, RB}},
 {"ps_muls1",	A  (4,	13,0),	AFRB_MASK,   PPCPS,	0,		{FRT, FRA, FRC}},
 {"ps_muls1.",	A  (4,	13,1),	AFRB_MASK,   PPCPS,	0,		{FRT, FRA, FRC}},
+{"rldixor",	VXASH(4,26),	VXASH_MASK,  POWER9,	0,		{RA, RS, SH6, RB}},
 {"ps_madds0",	A  (4,	14,0),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"ps_madds0.",	A  (4,	14,1),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"ps_madds1",	A  (4,	15,0),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
@@ -3180,6 +3203,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ps_msub.",	A  (4,	28,1),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"ps_madd",	A  (4,	29,0),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"ps_madd.",	A  (4,	29,1),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
+{"xor3",	VXA(4,	54),	VXA_MASK,    POWER9,	0,		{RA, RS, RB, RC}},
+{"nandxor",	VXA(4,	55),	VXA_MASK,    POWER9,	0,		{RA, RS, RB, RC}},
 {"vpermr",	VXA(4,	59),	VXA_MASK,    PPCVEC3,	0,		{VD, VA, VB, VC}},
 {"ps_nmsub",	A  (4,	30,0),	A_MASK,	     PPCPS,	0,		{FRT, FRA, FRC, FRB}},
 {"vaddeuqm",	VXA(4,	60),	VXA_MASK,    PPCVEC2,	0,		{VD, VA, VB, VC}},
@@ -4918,7 +4943,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dcbfep",	XRT(31,127,0),	XRT_MASK, E500MC|PPCA2, 0,		{RA0, RB}},
 
-{"setb",	X(31,128),    XRB_MASK|(3<<16), POWER9, 0,		{RT, BFA}},
+{"setb",	VX(31,256),  VXVB_MASK|(3<<16), POWER9,	0,		{RT, BFA}},
+{"setbool",	VX(31,257),  VXVB_MASK,         POWER9,	0,		{RT, BA}},
 
 {"wrtee",	X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0,	{RS}},
 
@@ -4968,6 +4994,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"prtyw",	X(31,154),    XRB_MASK, POWER6|PPCA2|PPC476, 0,		{RA, RS}},
 
+{"brw",		X(31,155),	XRB_MASK,    POWER9,	0,		{RA, RS}},
+
 {"stdepx",	X(31,157),	X_MASK,	  E500MC|PPCA2, 0,		{RS, RA0, RB}},
 
 {"stwepx",	X(31,159),	X_MASK,	  E500MC|PPCA2, 0,		{RS, RA0, RB}},
@@ -5005,6 +5033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"prtyd",	X(31,186),	XRB_MASK, POWER6|PPCA2,	0,		{RA, RS}},
 
+{"brd",		X(31,187),	XRB_MASK,    POWER9,	0,		{RA, RS}},
+
 {"cmprb",	X(31,192),	XCMP_MASK,   POWER9,	0,		{BF, L, RA, RB}},
 
 {"icblq.",	XRC(31,198,1),	X_MASK,	     E6500,	0,		{CT, RA0, RB}},
@@ -5043,6 +5073,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sleq",	XRC(31,217,0),	X_MASK,	     M601,	0,		{RA, RS, RB}},
 {"sleq.",	XRC(31,217,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
 
+{"brh",		X(31,219),	XRB_MASK,    POWER9,	0,		{RA, RS}},
+
 {"stbepx",	X(31,223),	X_MASK,	  E500MC|PPCA2, 0,		{RS, RA0, RB}},
 
 {"cmpeqb",	X(31,224),	XCMPL_MASK,  POWER9,	0,		{BF, RA, RB}},
@@ -6914,6 +6946,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mffs",	XRC(63,583,0),	XRARB_MASK,  COM,	PPCEFS|PPCVLE,	{FRT}},
 {"mffs.",	XRC(63,583,1),	XRARB_MASK,  COM,	PPCEFS|PPCVLE,	{FRT}},
 
+{"mffsce",	XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE,	{FRT}},
+{"mffscdrn",	XMMF(63,583,2,4), XMMF_MASK,         POWER9, PPCVLE,	{FRT, FRB}},
+{"mffscdrni",	XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE,	{FRT, DRM}},
+{"mffscrn",	XMMF(63,583,2,6), XMMF_MASK,         POWER9, PPCVLE,	{FRT, FRB}},
+{"mffscrni",	XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE,	{FRT, RM}},
+{"mffsl",	XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE,	{FRT}},
+
 {"dcmpuq",	X(63,642),	X_MASK,	     POWER6,	PPCVLE,		{BF, FRAp, FRBp}},
 
 {"xscmpuqp",	X(63,644),	XBF_MASK,    PPCVSX3,	PPCVLE,		{BF, VA, VB}},
diff --git a/gas/testsuite/gas/ppc/power9.d b/gas/testsuite/gas/ppc/power9.d
index 0c86898..1135d26 100644
--- a/gas/testsuite/gas/ppc/power9.d
+++ b/gas/testsuite/gas/ppc/power9.d
@@ -280,6 +280,14 @@ Disassembly of section \.text:
 .*:	(7f a8 49 80|80 49 a8 7f) 	cmprb   cr7,1,r8,r9
 .*:	(7d e0 01 00|00 01 e0 7d) 	setb    r15,cr0
 .*:	(7d fc 01 00|00 01 fc 7d) 	setb    r15,cr7
+.*:	(7e 00 01 01|01 01 00 7e) 	setbool r16,lt
+.*:	(7e 01 01 01|01 01 01 7e) 	setbool r16,gt
+.*:	(7e 02 01 01|01 01 02 7e) 	setbool r16,eq
+.*:	(7e 03 01 01|01 01 03 7e) 	setbool r16,so
+.*:	(7e 1c 01 01|01 01 1c 7e) 	setbool r16,4\*cr7\+lt
+.*:	(7e 1d 01 01|01 01 1d 7e) 	setbool r16,4\*cr7\+gt
+.*:	(7e 1e 01 01|01 01 1e 7e) 	setbool r16,4\*cr7\+eq
+.*:	(7e 1f 01 01|01 01 1f 7e) 	setbool r16,4\*cr7\+so
 .*:	(7f 40 52 1a|1a 52 40 7f) 	lxvl    vs26,0,r10
 .*:	(7f 14 52 1b|1b 52 14 7f) 	lxvl    vs56,r20,r10
 .*:	(7f 60 5b 1a|1a 5b 60 7f) 	stxvl   vs27,0,r11
@@ -392,4 +400,22 @@ Disassembly of section \.text:
 .*:	(7e b6 b9 55|55 b9 b6 7e) 	addex\.  r21,r22,r23,0
 .*:	(7e b6 bb 55|55 bb b6 7e) 	addex\.  r21,r22,r23,1
 .*:	(7e b6 bd 55|55 bd b6 7e) 	addex\.  r21,r22,r23,2
+.*:	(ff 20 04 8e|8e 04 20 ff) 	mffs    f25
+.*:	(ff 20 04 8f|8f 04 20 ff) 	mffs\.   f25
+.*:	(ff 41 04 8e|8e 04 41 ff) 	mffsce  f26
+.*:	(ff 74 a4 8e|8e a4 74 ff) 	mffscdrn f27,f20
+.*:	(ff 95 04 8e|8e 04 95 ff) 	mffscdrni f28,0
+.*:	(ff 95 3c 8e|8e 3c 95 ff) 	mffscdrni f28,7
+.*:	(ff b6 ac 8e|8e ac b6 ff) 	mffscrn f29,f21
+.*:	(ff d7 04 8e|8e 04 d7 ff) 	mffscrni f30,0
+.*:	(ff d7 1c 8e|8e 1c d7 ff) 	mffscrni f30,3
+.*:	(ff f8 04 8e|8e 04 f8 ff) 	mffsl   f31
+.*:	(7e 8a 01 76|76 01 8a 7e) 	brd     r10,r20
+.*:	(7e ab 01 b6|b6 01 ab 7e) 	brh     r11,r21
+.*:	(7e cc 01 36|36 01 cc 7e) 	brw     r12,r22
+.*:	(11 6a 63 77|77 63 6a 11) 	nandxor r10,r11,r12,r13
+.*:	(12 b4 b5 f6|f6 b5 b4 12) 	xor3    r20,r21,r22,r23
+.*:	(11 6a 60 34|34 60 6a 11) 	rldixor r10,r11,0,r12
+.*:	(11 6a 66 f4|f4 66 6a 11) 	rldixor r10,r11,27,r12
+.*:	(11 6a 67 f5|f5 67 6a 11) 	rldixor r10,r11,63,r12
 #pass
diff --git a/gas/testsuite/gas/ppc/power9.s b/gas/testsuite/gas/ppc/power9.s
index 8d33d6c..21edb9c 100644
--- a/gas/testsuite/gas/ppc/power9.s
+++ b/gas/testsuite/gas/ppc/power9.s
@@ -271,6 +271,14 @@ power9:
 	cmprb       7,1,8,9
 	setb        15,0
 	setb        15,7
+	setbool     16,0
+	setbool     16,1
+	setbool     16,2
+	setbool     16,3
+	setbool     16,28
+	setbool     16,29
+	setbool     16,30
+	setbool     16,31
 	lxvl        26,0,10
 	lxvl        56,20,10
 	stxvl       27,0,11
@@ -383,3 +391,21 @@ power9:
 	addex.      21,22,23,0
 	addex.      21,22,23,1
 	addex.      21,22,23,2
+	mffs        25
+	mffs.       25
+	mffsce      26
+	mffscdrn    27,20
+	mffscdrni   28,0
+	mffscdrni   28,7
+	mffscrn     29,21
+	mffscrni    30,0
+	mffscrni    30,3
+	mffsl       31
+	brd         10,20
+	brh         11,21
+	brw         12,22
+	nandxor     10,11,12,13
+	xor3        20,21,22,23
+	rldixor     10,11,0,12
+	rldixor     10,11,27,12
+	rldixor     10,11,63,12


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