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[PATCH] gas/opcodes: Add initial arc nps400 support
- From: Andrew Burgess <andrew dot burgess at embecosm dot com>
- To: binutils at sourceware dot org
- Cc: noamca at mellanox dot com, Claudiu dot Zissulescu at synopsys dot com, Cupertino dot Miranda at synopsys dot com, Andrew Burgess <andrew dot burgess at embecosm dot com>
- Date: Thu, 25 Feb 2016 23:39:14 +0000
- Subject: [PATCH] gas/opcodes: Add initial arc nps400 support
- Authentication-results: sourceware.org; auth=none
The ARC NPS400 is an ARC700 with some additional instructions, created
by Mellanox (formally EZchip). This commit adds initial support for the
ARC NPS400 variant.
At this stage I have added only one new instruction, movb, this is to
allow a discussion of the correct approach for adding additional
instructions to the arc target. Additional instructions, and supporting
relocations will be added in future commits.
When binutils is configured for NPS400, by specifying 'mellanox' as the
vendor name in the target tuple, then the additional NPS400 instructions
are added into the ARC700 instruction set (within the opcodes library),
and in the assembler, the default architecture is changed to be ARC700.
There's a test for the new instruction, a test for the default
architecture, and one test needs updating slightly.
gas/ChangeLog:
* config.in: Regenerate.
* config/tc-arc.c (arc_target): Don't provide an initial value.
(arc_target_name): Likewise.
(arc_features): Likewise.
(arc_mach_type): Likewise.
(arc_select_cpu): New function.
(md_begin): Call arc_select_cpu.
(md_parse_option): Move initialisation into arc_select_cpu.
* configure: Regenerate.
* configure.ac: Detect mellanox arc target.
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_dst): New function.
(extract_nps_dst): New function.
(insert_nps_j_dst): New function.
(extract_nps_j_dst): New function.
(insert_nps_dup_src1): New function.
(extract_nps_dup_src1): New function.
(insert_nps_src2): New function.
(extract_nps_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 entries.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Detect NPS400 ARC target.
binutils/ChangeLog:
* testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700.
---
binutils/ChangeLog | 4 +
binutils/testsuite/binutils-all/objdump.exp | 2 +-
gas/ChangeLog | 17 +++
gas/config.in | 3 +
gas/config/tc-arc.c | 92 ++++++-----
gas/configure | 10 ++
gas/configure.ac | 8 +
gas/testsuite/gas/arc/nps400-0.d | 16 ++
gas/testsuite/gas/arc/nps400-0.s | 2 +
gas/testsuite/gas/arc/nps400-1.d | 15 ++
gas/testsuite/gas/arc/nps400-1.s | 7 +
opcodes/ChangeLog | 22 +++
opcodes/arc-nps400-tbl.h | 3 +
opcodes/arc-opc.c | 229 ++++++++++++++++++++++++++++
opcodes/config.in | 3 +
opcodes/configure | 8 +
opcodes/configure.ac | 6 +
17 files changed, 405 insertions(+), 42 deletions(-)
create mode 100644 gas/testsuite/gas/arc/nps400-0.d
create mode 100644 gas/testsuite/gas/arc/nps400-0.s
create mode 100644 gas/testsuite/gas/arc/nps400-1.d
create mode 100644 gas/testsuite/gas/arc/nps400-1.s
create mode 100644 opcodes/arc-nps400-tbl.h
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index bbaa373..4026d0d 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/binutils-all/objdump.exp (cpus_expected): Add ARC700.
+
2016-02-16 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/19647
diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp
index 22c4686..eb4d5f4 100644
--- a/binutils/testsuite/binutils-all/objdump.exp
+++ b/binutils/testsuite/binutils-all/objdump.exp
@@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
set cpus_expected [list]
-lappend cpus_expected aarch64 alpha arc ARCv2 arm cris
+lappend cpus_expected aarch64 alpha arc ARCv2 ARC700 arm cris
lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 0e9222e..6655ff7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,20 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config.in: Regenerate.
+ * config/tc-arc.c (arc_target): Don't provide an initial value.
+ (arc_target_name): Likewise.
+ (arc_features): Likewise.
+ (arc_mach_type): Likewise.
+ (arc_select_cpu): New function.
+ (md_begin): Call arc_select_cpu.
+ (md_parse_option): Move initialisation into arc_select_cpu.
+ * configure: Regenerate.
+ * configure.ac: Detect mellanox arc target.
+ * testsuite/gas/arc/nps400-0.d: New file.
+ * testsuite/gas/arc/nps400-0.s: New file.
+ * testsuite/gas/arc/nps400-1.d: New file.
+ * testsuite/gas/arc/nps400-1.s: New file.
+
2016-02-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* as.c (select_emulation_mode): Add const qualifiers.
diff --git a/gas/config.in b/gas/config.in
index 8b040fc..3462912 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -13,6 +13,9 @@
/* Define if using AIX 5.2 value for C_WEAKEXT. */
#undef AIX_WEAK_SUPPORT
+/* ARC NPS400 support. */
+#undef ARC_NPS400
+
/* assert broken? */
#undef BROKEN_ASSERT
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 82cff9a..70afb81 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -310,13 +310,14 @@ static void assemble_insn
(const struct arc_opcode *, const expressionS *, int,
const struct arc_flags *, int, struct arc_insn *);
-/* The cpu for which we are generating code. */
-static unsigned arc_target = ARC_OPCODE_BASE;
-static const char *arc_target_name = "<all>";
-static unsigned arc_features = 0x00;
+/* The cpu for which we are generating code. These are initialised either
+ by command line options, or set to a sane default in md_begin. */
+static unsigned arc_target;
+static const char *arc_target_name;
+static unsigned arc_features;
/* The default architecture. */
-static int arc_mach_type = bfd_mach_arc_arcv2;
+static int arc_mach_type;
/* Non-zero if the cpu type has been explicitly specified. */
static int mach_type_specified_p = 0;
@@ -569,6 +570,40 @@ md_number_to_chars_midend (char *buf, valueT val, int n)
}
}
+/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
+ the relevant static global variables. */
+
+static void
+arc_select_cpu (const char *arg)
+{
+ int cpu_flags = EF_ARC_CPU_GENERIC;
+ int i;
+ char *dst, *cpu = alloca (strlen (arg) + 1);
+ const char *src;
+
+ for (dst = cpu, src = arg; *src != '\0'; ++dst, ++src)
+ *dst = TOLOWER (*src);
+
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ if (!strcmp (cpu_types[i].name, cpu))
+ {
+ arc_target = cpu_types[i].flags;
+ arc_target_name = cpu_types[i].name;
+ arc_features = cpu_types[i].features;
+ arc_mach_type = cpu_types[i].mach;
+ cpu_flags = cpu_types[i].eflags;
+ break;
+ }
+ }
+
+ if (!cpu_types[i].name)
+ as_fatal (_("unknown architecture: %s\n"), arg);
+
+ if (cpu_flags != EF_ARC_CPU_GENERIC)
+ arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
+}
+
/* Here ends all the ARCompact extension instruction assembling
stuff. */
@@ -2067,6 +2102,15 @@ md_begin (void)
{
unsigned int i;
+ if (!mach_type_specified_p)
+ {
+#ifdef ARC_NPS400
+ arc_select_cpu ("arc700");
+#else
+ arc_select_cpu ("all");
+#endif
+ }
+
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2853,8 +2897,6 @@ arc_parse_name (const char *name,
int
md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
{
- int cpu_flags = EF_ARC_CPU_GENERIC;
-
switch (c)
{
case OPTION_ARC600:
@@ -2872,37 +2914,8 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
case OPTION_MCPU:
{
- int i;
- char *s = alloca (strlen (arg) + 1);
-
- {
- char *t = s;
- char *arg1 = arg;
-
- do
- *t = TOLOWER (*arg1++);
- while (*t++);
- }
-
- for (i = 0; cpu_types[i].name; ++i)
- {
- if (!strcmp (cpu_types[i].name, s))
- {
- arc_target = cpu_types[i].flags;
- arc_target_name = cpu_types[i].name;
- arc_features = cpu_types[i].features;
- arc_mach_type = cpu_types[i].mach;
- cpu_flags = cpu_types[i].eflags;
-
- mach_type_specified_p = 1;
- break;
- }
- }
-
- if (!cpu_types[i].name)
- {
- as_fatal (_("unknown architecture: %s\n"), arg);
- }
+ arc_select_cpu (arg);
+ mach_type_specified_p = 1;
break;
}
@@ -2956,9 +2969,6 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
return 0;
}
- if (cpu_flags != EF_ARC_CPU_GENERIC)
- arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
-
return 1;
}
diff --git a/gas/configure b/gas/configure
index cd7182f..be39ffa 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12160,6 +12160,16 @@ _ACEOF
# Other random stuff.
case ${cpu_type} in
+ arc)
+ case ${target} in
+ arc*-mellanox-*)
+
+$as_echo "#define ARC_NPS400 1" >>confdefs.h
+
+ ;;
+ esac
+ ;;
+
mips)
# Set mips_cpu to the name of the default CPU.
case ${target_cpu} in
diff --git a/gas/configure.ac b/gas/configure.ac
index 377526e..d72ecd4 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -234,6 +234,14 @@ changequote([,])dnl
# Other random stuff.
case ${cpu_type} in
+ arc)
+ case ${target} in
+ arc*-mellanox-*)
+ AC_DEFINE(ARC_NPS400, 1, [ARC NPS400 support.])
+ ;;
+ esac
+ ;;
+
mips)
# Set mips_cpu to the name of the default CPU.
case ${target_cpu} in
diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
new file mode 100644
index 0000000..09e62b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -0,0 +1,16 @@
+#as:
+#target: arc*-mellanox-*
+#readelf: -h
+
+#...
+ Class: ELF32
+ Data: 2's complement, .* endian
+ Version: 1 \(current\)
+ OS/ABI: UNIX - System V
+ ABI Version: 0
+ Type: REL \(Relocatable file\)
+ Machine: ARCompact
+ Version: 0x1
+#...
+ Flags: 0x303, ARC 700, v3 no-legacy-syscalls ABI
+#...
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s
new file mode 100644
index 0000000..2b6cc1d
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.s
@@ -0,0 +1,2 @@
+ .text
+ nop
diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
new file mode 100644
index 0000000..bd68eb0
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -0,0 +1,15 @@
+#as: -mcpu=arc700
+#target: arc*-mellanox-*
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6
+ 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6
+ 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6
+ c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6
+ 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6
+ 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6
diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s
new file mode 100644
index 0000000..1d340b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.s
@@ -0,0 +1,7 @@
+ .text
+ movb r0, r0, r1, 4, 5, 6
+ movb r0, r0, r12, 4, 5, 6
+ movb r15, r15, r12, 4, 5, 6
+ movb.cl r0, r1, 4, 5, 6
+ movb.cl r0, r14, 4, 5, 6
+ movb.cl r13, r1, 4, 5, 6
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f95fd6a..dca02cb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,25 @@
+2016-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_dst): New function.
+ (extract_nps_dst): New function.
+ (insert_nps_j_dst): New function.
+ (extract_nps_j_dst): New function.
+ (insert_nps_dup_src1): New function.
+ (extract_nps_dup_src1): New function.
+ (insert_nps_src2): New function.
+ (extract_nps_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 entries.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * configure.ac: Detect NPS400 ARC target.
+
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
new file mode 100644
index 0000000..27207b1
--- /dev/null
+++ b/opcodes/arc-nps400-tbl.h
@@ -0,0 +1,3 @@
+/* movb<.f><.cl> */
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_J_DST, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..398fecb 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -26,6 +26,12 @@
#include "opintl.h"
#include "libiberty.h"
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+ instructions. Support for this target is available when binutils is
+ configured and built for the 'arc*-mellanox-*-*' target. As far as
+ possible all ARC NPS400 features are built into all ARC target builds as
+ this reduces the chances that regressions might creep in. */
+
/* Insert RB register into a 32-bit opcode. */
static unsigned
insert_rb (unsigned insn,
@@ -637,6 +643,188 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
return value;
}
+/* ARC NPS400 Support: See comment near head of file. */
+static unsigned
+insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_j_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_j_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is not set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_dup_src1 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_dup_src1 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value;
+
+ /* If the CL flag is set then this is invalid. */
+ if (((insn >> 15) & 0x1) == 0x1)
+ *invalid = TRUE;
+ value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 21;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 21;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
+ return insn;
+}
+
+static int
+extract_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 21) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 1 || value > 32)
+ {
+ *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+ return insn;
+ }
+
+ --value;
+ insn |= ((value & 0x1f) << 10);
+ return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x1f) + 1;
+}
+
/* Include the generic extract/insert functions. Order is important
as some of the functions present in the .h may be disabled via
defines. */
@@ -795,6 +983,13 @@ const struct arc_flag_operand arc_flag_operands[] =
/* Fake Flags. */
#define F_NE (F_H17 + 1)
{ "ne", 0, 0, 0, 1 },
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define F_NPS_CL (F_NE + 1)
+ { "cl", 1, 1, 15, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+ { "f", 1, 1, 20, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -865,6 +1060,13 @@ const struct arc_flag_class arc_flag_classes[] =
#define C_NE (C_AS + 1)
{ CND, { F_NE, F_NULL}},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define C_NPS_CL (C_NE + 1)
+ { FLG, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F (C_NPS_CL + 1)
+ { FLG, { F_NPS_FLAG, F_NULL}},
};
/* The operands table.
@@ -1183,6 +1385,29 @@ const struct arc_operand arc_operands[] =
/* UIMM6_5_S mask = 0000011111100000. */
#define UIMM6_5_S (W6 + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst },
+
+#define NPS_R_J_DST (NPS_R_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_j_dst, extract_nps_j_dst },
+
+#define NPS_R_SRC1 (NPS_R_J_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_dup_src1, extract_nps_dup_src1 },
+
+#define NPS_R_SRC2 (NPS_R_SRC1 + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_src2, extract_nps_src2 },
+
+ /* Next 3 operands are integer immediate for bitops. */
+#define NPS_BITOP_DST_POS (NPS_R_SRC2 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -1198,6 +1423,10 @@ const unsigned arc_NToperand = FKT_NT;
const struct arc_opcode arc_opcodes[] =
{
#include "arc-tbl.h"
+
+#ifdef ARC_NPS400
+#include "arc-nps400-tbl.h"
+#endif
};
const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
diff --git a/opcodes/config.in b/opcodes/config.in
index 55a80fd..34b194a 100644
--- a/opcodes/config.in
+++ b/opcodes/config.in
@@ -7,6 +7,9 @@
#endif
#define __CONFIG_H__ 1
+/* ARC NPS400 support. */
+#undef ARC_NPS400
+
/* Define to 1 if translation of program messages to the user's native
language is requested. */
#undef ENABLE_NLS
diff --git a/opcodes/configure b/opcodes/configure
index 75c6573..258c963 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12505,6 +12505,14 @@ fi
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+
+$as_echo "#define ARC_NPS400 1" >>confdefs.h
+
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index c7f4783..1dbe70b 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -210,6 +210,12 @@ AC_SUBST(SHARED_DEPENDENCIES)
# target-specific stuff:
+case ${target} in
+ arc*-mellanox-*)
+ AC_DEFINE(ARC_NPS400, 1, [ARC NPS400 support.])
+ ;;
+esac
+
# Canonicalize the secondary target names.
if test -n "$enable_targets" ; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
--
2.6.4