This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.


ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.

The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.

The general form for these instructions is
   <OP> <Hd>, <V>.<T>
   where T is 4h or 8h.

The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
	instructions.
        * gas/aarch64/illegal.d: Update expected output.
        * gas/aarch64/illegal.s: Replace test for illegal use of 'h'
	specifier.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_XLANES_FP_H): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
	fminnmv, fminv to the Adv.SIMD across lanes group.

>From dd4c51468ac18179debeec43e33f29a1a123a09f Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 10 Sep 2015 16:18:37 +0100
Subject: [PATCH 08/14] [AArch64] Add FP16 Adv.SIMD across lanes instructions
 (VII).

Change-Id: Ifadc9c67bb3fd464b853ce7eafe480b0812e602b
---
 gas/testsuite/gas/aarch64/advsimd-fp16.d |   20 +
 gas/testsuite/gas/aarch64/advsimd-fp16.s |   16 +
 gas/testsuite/gas/aarch64/illegal.l      |    4 +-
 gas/testsuite/gas/aarch64/illegal.s      |    4 +-
 opcodes/aarch64-asm-2.c                  |  682 ++++----
 opcodes/aarch64-dis-2.c                  | 2568 +++++++++++++++---------------
 opcodes/aarch64-opc-2.c                  |  106 +-
 opcodes/aarch64-tbl.h                    |   15 +
 8 files changed, 1755 insertions(+), 1660 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index dacd51b..241dc3f 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -472,3 +472,23 @@ Disassembly of section \.text:
  [0-9a-f]+:	7fa39041 	fmulx	s1, s2, v3.s\[1\]
  [0-9a-f]+:	7f139041 	fmulx	h1, h2, v3.h\[1\]
  [0-9a-f]+:	7f009000 	fmulx	h0, h0, v0.h\[0\]
+ [0-9a-f]+:	6e30c841 	fmaxnmv	s1, v2.4s
+ [0-9a-f]+:	0e30c841 	fmaxnmv	h1, v2.4h
+ [0-9a-f]+:	4e30c841 	fmaxnmv	h1, v2.8h
+ [0-9a-f]+:	0e30c800 	fmaxnmv	h0, v0.4h
+ [0-9a-f]+:	4e30c800 	fmaxnmv	h0, v0.8h
+ [0-9a-f]+:	6e30f841 	fmaxv	s1, v2.4s
+ [0-9a-f]+:	0e30f841 	fmaxv	h1, v2.4h
+ [0-9a-f]+:	4e30f841 	fmaxv	h1, v2.8h
+ [0-9a-f]+:	0e30f800 	fmaxv	h0, v0.4h
+ [0-9a-f]+:	4e30f800 	fmaxv	h0, v0.8h
+ [0-9a-f]+:	6eb0c841 	fminnmv	s1, v2.4s
+ [0-9a-f]+:	0eb0c841 	fminnmv	h1, v2.4h
+ [0-9a-f]+:	4eb0c841 	fminnmv	h1, v2.8h
+ [0-9a-f]+:	0eb0c800 	fminnmv	h0, v0.4h
+ [0-9a-f]+:	4eb0c800 	fminnmv	h0, v0.8h
+ [0-9a-f]+:	6eb0f841 	fminv	s1, v2.4s
+ [0-9a-f]+:	0eb0f841 	fminv	h1, v2.4h
+ [0-9a-f]+:	4eb0f841 	fminv	h1, v2.8h
+ [0-9a-f]+:	0eb0f800 	fminv	h0, v0.4h
+ [0-9a-f]+:	4eb0f800 	fminv	h0, v0.8h
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index 10f9067..c4e0ad1 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -187,3 +187,19 @@
 
 	sindexed_elem fmul
 	sindexed_elem fmulx
+
+	/* Adv.SIMD across lanes.  */
+
+	.macro across_lanes, op
+	\op	s1, v2.4s
+	\op	h1, v2.4h
+	\op	h1, v2.8h
+	\op	h0, v0.4h
+	\op	h0, v0.8h
+	.endm
+
+	across_lanes fmaxnmv
+	across_lanes fmaxv
+	across_lanes fminnmv
+	across_lanes fminv
+
diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 0e8c7eb..7482bc7 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -8,8 +8,8 @@
 [^:]*:32: Error: .*`saddlv q7,v31.2d'
 [^:]*:33: Error: .*`smaxv s7,v31.2s'
 [^:]*:34: Error: .*`sminv d7,v31.2d'
-[^:]*:35: Error: .*`fmaxv h7,v31.8h'
-[^:]*:36: Error: .*`fmaxv h7,v31.4h'
+[^:]*:35: Error: .*`fmaxv h7,v31.2h'
+[^:]*:36: Error: .*`fmaxv s7,v31.4h'
 [^:]*:37: Error: .*`fminv d7,v31.2d'
 [^:]*:39: Error: .*`abs b0,b31'
 [^:]*:40: Error: .*`neg b0,b31'
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index 718f7ed..0960b7e 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -32,8 +32,8 @@
 	saddlv	q7, v31.2d
 	smaxv	s7, v31.2s
 	sminv	d7, v31.2d
-	fmaxv	h7, v31.8h
-	fmaxv	h7, v31.4h
+	fmaxv	h7, v31.2h
+	fmaxv	s7, v31.4h
 	fminv	d7, v31.2d
 
 	abs b0, b31
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 147e3f3..12b44f3 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1218,6 +1218,13 @@
   QLF2(S_S, V_4S),		\
 }
 
+/* e.g. FMINV <V><d>, <Vn>.<T>.  */
+#define QL_XLANES_FP_H		\
+{				\
+  QLF2 (S_H, V_4H),		\
+  QLF2 (S_H, V_8H),		\
+}
+
 /* e.g. SADDLV <V><d>, <Vn>.<T>.  */
 #define QL_XLANES_L		\
 {				\
@@ -1391,9 +1398,17 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
   {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
   {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+  {"fmaxnmv", 0xe30c800, 0xbffffc00, asimdall, 0, SIMD_F16,
+   OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
   {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+  {"fmaxv", 0xe30f800, 0xbffffc00, asimdall, 0, SIMD_F16,
+   OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
   {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+  {"fminnmv", 0xeb0c800, 0xbffffc00, asimdall, 0, SIMD_F16,
+   OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
   {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
+  {"fminv", 0xeb0f800, 0xbffffc00, asimdall, 0, SIMD_F16,
+   OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
   /* AdvSIMD three different.  */
   {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
   {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
-- 
2.1.4


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]